Statistic based cache pre-fetcher

    公开(公告)号:US11983116B2

    公开(公告)日:2024-05-14

    申请号:US17973427

    申请日:2022-10-25

    CPC classification number: G06F12/0862 G06F9/321 G06F12/0811

    Abstract: The disclosure relates to technology for pre-fetching data. An apparatus comprises a processor core, pre-fetch logic, and a memory hierarchy. The pre-fetch logic is configured to generate cache pre-fetch requests for a program instruction identified by a program counter. The pre-fetch logic is configured to track one or more statistics with respect to the cache pre-fetch requests. The pre-fetch logic is configured to link the one or more statistics with the program counter. The pre-fetch logic is configured to determine a degree of the cache pre-fetch requests for the program instruction based on the one or more statistics. The memory hierarchy comprises main memory and a hierarchy of caches. The memory hierarchy further comprises a memory controller configured to pre-fetch memory blocks identified in the cache pre-fetch requests from a current level in the memory hierarchy into a higher level of the memory hierarchy.

    Data Management Method, Apparatus, and System, and Storage Medium

    公开(公告)号:US20230259462A1

    公开(公告)日:2023-08-17

    申请号:US18298006

    申请日:2023-04-10

    CPC classification number: G06F12/1408 H04L9/14 G06F2212/1052

    Abstract: A data management method comprises a first processing node that obtains a secure storage key based on a first external keying material corresponding to the first processing node, encrypts data corresponding to an application program in the first processing node, and sends encrypted data to a second processing node. The second processing node obtains a secure storage key based on a second external keying material corresponding to the second processing node, and decrypts the encrypted data that corresponds to the application program and that is sent by the first processing node. The second external keying material is the same as the first external keying material, whereby the second processing node and the first processing node may obtain a same secure storage key, and the second processing node may successfully decrypt the encrypted data that corresponds to the application program and that is sent by the first processing node.

    Method, apparatus, and system for retransmitting data packet in quick path interconnect system
    3.
    发明授权
    Method, apparatus, and system for retransmitting data packet in quick path interconnect system 有权
    用于在快速路径互连系统中重传数据包的方法,装置和系统

    公开(公告)号:US09197373B2

    公开(公告)日:2015-11-24

    申请号:US14107109

    申请日:2013-12-16

    Abstract: The present invention discloses a method for retransmitting a data packet in a quick path interconnect system, and a node. When a first node serves as a sending end, only the first data packet detected to be faulty is retransmitted to a second node, thereby saving system resources that need to be occupied in the data packet retransmission. When the first node serves as a receiving end, it implements that the packet loss does not occur in the first node in a case that the second node only retransmits the second data packet detected to be faulty, thereby ensuring reliability of the data packet transmission based on the QPI bus.

    Abstract translation: 本发明公开了一种在快速路径互连系统和节点中重传数据分组的方法。 当第一节点用作发送端时,只有检测到有故障的第一数据包被重传到第二节点,从而节省了在数据分组重传中需要占用的系统资源。 当第一节点用作接收端时,在第二节点仅重发检测到的第二数据包有故障的情况下,实现第一节点中不发生分组丢失,从而确保基于数据分组传输的可靠性 在QPI总线上。

    Method and apparatus of data migration based on use algorithm

    公开(公告)号:US11809732B2

    公开(公告)日:2023-11-07

    申请号:US17893499

    申请日:2022-08-23

    Inventor: Jin Xie Gang Liu

    CPC classification number: G06F3/0647 G06F3/061 G06F3/067

    Abstract: A memory data migration method, apparatus, and system are provided. During memory migration, data is classified into two parts based on a hot and cold degree of the data. Hot data is directly migrated, and cold data is written into a shared storage device shared by memories. When needing to be used in a destination-end memory, the cold data may be read from the shared storage device. This reduces an amount of data that needs to be migrated to the destination-end memory, thereby improving memory migration efficiency.

    CPU and multi-CPU system management method

    公开(公告)号:US11138147B2

    公开(公告)日:2021-10-05

    申请号:US15692359

    申请日:2017-08-31

    Abstract: The present disclosure provides a multi-CPU system, where the multi-CPU system includes: at least two Quick-Path Interconnect QPI domains, a first node controller NC group, and a second node controller NC group; according to a CPU route configuration, there is at least one CPU that can access a CPU in another QPI domain by using the first NC group; and there is at least one CPU that can access a CPU in another QPI domain by using the second NC group. According to this topology, hot swap of an NC can be implemented while the system is relatively slightly affected.

    CPU AND MULTI-CPU SYSTEM MANAGEMENT METHOD
    7.
    发明申请

    公开(公告)号:US20170364475A1

    公开(公告)日:2017-12-21

    申请号:US15692359

    申请日:2017-08-31

    CPC classification number: G06F15/8023 G06F15/173 G06F15/17343

    Abstract: The present disclosure provides a multi-CPU system, where the multi-CPU system includes: at least two Quick-Path Interconnect QPI domains, a first node controller NC group, and a second node controller NC group; according to a CPU route configuration, there is at least one CPU that can access a CPU in another QPI domain by using the first NC group; and there is at least one CPU that can access a CPU in another QPI domain by using the second NC group. According to this topology, hot swap of an NC can be implemented while the system is relatively slightly affected.

    Method for accessing cache and pseudo cache agent
    9.
    发明授权
    Method for accessing cache and pseudo cache agent 有权
    访问缓存和伪高速缓存代理的方法

    公开(公告)号:US09465743B2

    公开(公告)日:2016-10-11

    申请号:US13719626

    申请日:2012-12-19

    CPC classification number: G06F12/084 G06F12/0806 G06F12/0811 G06F2212/1012

    Abstract: Embodiments of the present invention disclose a method for accessing a cache and a pseudo cache agent (PCA). The method of the present invention is applied to a multiprocessor system, where the system includes at least one NC, at least one PCA conforming to a processor micro-architecture level interconnect protocol is embedded in the NC, the PCA is connected to at least one PCA storage device, and the PCA storage device stores data shared among memories in the multiprocessor system. The method of the present invention includes: if the NC receives a data request, obtaining, by the PCA, target data required in the data request from the PCA storage device connected to the PCA; and sending the target data to a sender of the data request. Embodiments of the present invention are mainly applied to a process of accessing cache data in the multiprocessor system.

    Abstract translation: 本发明的实施例公开了一种用于访问高速缓存和伪高速缓存代理(PCA)的方法。 本发明的方法应用于多处理器系统,其中系统包括至少一个NC,至少一个符合处理器微架构级互连协议的PCA嵌入在NC中,PCA连接到至少一个 PCA存储装置,PCA存储装置将存储在多处理器系统中的数据共享。 本发明的方法包括:如果NC接收到数据请求,则由PCA从连接到PCA的PCA存储设备获得数据请求中所需的目标数据; 并将目标数据发送到数据请求的发送者。 本发明的实施例主要应用于在多处理器系统中访问高速缓存数据的过程。

Patent Agency Ranking