公开(公告)号：US11983116B2

公开(公告)日：2024-05-14

申请号：US17973427

申请日：2022-10-25

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sang Wook Do ,  Wei-Yu Chen ,  Gang Liu

IPC: G06F12/0862 ,  G06F9/32 ,  G06F12/0811

CPC classification number: G06F12/0862 ,  G06F9/321 ,  G06F12/0811

Abstract: The disclosure relates to technology for pre-fetching data. An apparatus comprises a processor core, pre-fetch logic, and a memory hierarchy. The pre-fetch logic is configured to generate cache pre-fetch requests for a program instruction identified by a program counter. The pre-fetch logic is configured to track one or more statistics with respect to the cache pre-fetch requests. The pre-fetch logic is configured to link the one or more statistics with the program counter. The pre-fetch logic is configured to determine a degree of the cache pre-fetch requests for the program instruction based on the one or more statistics. The memory hierarchy comprises main memory and a hierarchy of caches. The memory hierarchy further comprises a memory controller configured to pre-fetch memory blocks identified in the cache pre-fetch requests from a current level in the memory hierarchy into a higher level of the memory hierarchy.

公开(公告)号：US12282429B2

公开(公告)日：2025-04-22

申请号：US17944031

申请日：2022-09-13

Applicant: Huawei Technologies Co., Ltd.

Inventor： Elnaz Ebrahimi ,  Ehsan Khish Ardestani Zadeh ,  Wei-Yu Chen ,  Liang Peng

IPC: G06F12/0862 ,  G06F12/0811

Abstract: An apparatus includes a processor core and a memory hierarchy. The memory hierarchy includes main memory and one or more caches between the main memory and the processor core. A plurality of hardware pre-fetchers are coupled to the memory hierarchy and a pre-fetch control circuit is coupled to the plurality of hardware pre-fetchers. The pre-fetch control circuit is configured to compare changes in one or more cache performance metrics over two or more sampling intervals and control operation of the plurality of hardware pre-fetchers in response to a change in one or more performance metrics between at least a first sampling interval and a second sampling interval.

公开(公告)号：US20230049662A1

公开(公告)日：2023-02-16

申请号：US17973427

申请日：2022-10-25

Applicant: Huawei Technologies Co., Ltd.

Inventor： Sang Wook Do ,  Wei-Yu Chen ,  Norris Liu

IPC: G06F12/0862 ,  G06F12/0811 ,  G06F9/32

Abstract: The disclosure relates to technology for pre-fetching data. An apparatus comprises a processor core, pre-fetch logic, and a memory hierarchy. The pre-fetch logic is configured to generate cache pre-fetch requests for a program instruction identified by a program counter. The pre-fetch logic is configured to track one or more statistics with respect to the cache pre-fetch requests. The pre-fetch logic is configured to link the one or more statistics with the program counter. The pre-fetch logic is configured to determine a degree of the cache pre-fetch requests for the program instruction based on the one or more statistics. The memory hierarchy comprises main memory and a hierarchy of caches. The memory hierarchy further comprises a memory controller configured to pre-fetch memory blocks identified in the cache pre-fetch requests from a current level in the memory hierarchy into a higher level of the memory hierarchy.

公开(公告)号：US20230022190A1

公开(公告)日：2023-01-26

申请号：US17944031

申请日：2022-09-13

Applicant: Huawei Technologies Co., Ltd.

Inventor： Elnaz Ebrahimi ,  Ehsan Khish Ardestani Zadeh ,  Wei-Yu Chen ,  Liang Peng

IPC: G06F12/0862 ,  G06F12/0811

Abstract: An apparatus includes a processor core and a memory hierarchy. The memory hierarchy includes main memory and one or more caches between the main memory and the processor core. A plurality of hardware pre-fetchers are coupled to the memory hierarchy and a pre-fetch control circuit is coupled to the plurality of hardware pre-fetchers. The pre-fetch control circuit is configured to compare changes in one or more cache performance metrics over two or more sampling intervals and control operation of the plurality of hardware pre-fetchers in response to a change in one or more performance metrics between at least a first sampling interval and a second sampling interval.