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公开(公告)号:US20230050442A1
公开(公告)日:2023-02-16
申请号:US17818123
申请日:2022-08-08
发明人: Yung Hsing Chu , Yen-Chun Chou , Shan-Hui Lin
IPC分类号: G01N21/88 , H01L21/304 , H01L21/67 , H01L21/66
摘要: A method for processing semiconductor wafers includes obtaining measurement data from a surface of a semiconductor wafer processed by a front-end process tool. The method includes determining a center plane of the wafer based on the measurement data, generating raw shape profiles, and generating ideal shape profiles. The method further includes generating Gapi profiles based on the raw shape profiles and the ideal shape profiles, and calculating a Gapi value of the semiconductor wafer based on the Gapi profiles. The generated Gapi profiles and/or the calculated Gapi value may be used to tune the front-end process tool and/or sort the semiconductor wafer for polishing. Systems include at least a front-end process tool, a flatness measurement tool, and a computing device.
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公开(公告)号:US20230047412A1
公开(公告)日:2023-02-16
申请号:US17818131
申请日:2022-08-08
发明人: Yung Hsing Chu , Yen-Chun Chou , Yau-Ching Yang , Jing Ru Hong , Shan-Hui Lin
摘要: A method for processing semiconductor wafers includes obtaining measurement data of an edge profile of a semiconductor wafer processed by a front-end process tool. The method includes determining an edge profile center point based on the measurement data, generating a raw height profile, and generating an ideal edge profile. The method further includes generating a Gapi edge profile of the semiconductor wafer based on the raw height profile and the ideal edge profile and calculating a Gapi edge value of the semiconductor wafer based on the Gapi edge profile. The generated Gapi edge profile and/or the calculated Gapi edge value may be used to tune the front-end process tool and/or sort the semiconductor wafer for polishing. Systems include at least a front-end process tool, a flatness measurement tool, and a computing device.
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公开(公告)号:US20220403549A1
公开(公告)日:2022-12-22
申请号:US17834807
申请日:2022-06-07
发明人: Zheng Lu , Shan-Hui Lin , Chun-Chin Tu , Chi-Yung Chen , Feng-Chien Tsai , Hong-Huei Huang
摘要: Methods for determining suitability of Czochralski growth conditions to produce silicon substrates for epitaxy. The methods involve evaluating substrates sliced from ingots grown under different growth conditions (e.g., impurity profiles) by imaging the wafer by infrared depolarization. An infrared depolarization parameter is generated for each epitaxial wafer. The parameters may be compared to determine which growth conditions are well-suited to produce substrates for epitaxial and/or post-epi heat treatments.
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公开(公告)号:US20220403548A1
公开(公告)日:2022-12-22
申请号:US17834804
申请日:2022-06-07
发明人: Shan-Hui Lin , Chun-Chin Tu , Zheng Lu
摘要: Methods for determining suitability of a silicon substrate for epitaxy and/or for determining slip resistance during epitaxy and post-epitaxy thermal treatment are disclosed. The methods involve evaluating different substrates of the epitaxial wafers by imaging the wafer by infrared depolarization. An infrared depolarization parameter is generated for each epitaxial wafer. The parameters may be compared to determine which substrates are well-suited for epitaxial and/or post-epi heat treatments.
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