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    Low power system on chip
    1.
    发明授权
    Low power system on chip 有权

    公开(公告)号：US12147263B2

    公开(公告)日：2024-11-19

    申请号：US17847636

    申请日：2022-06-23

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Kyuseung Han ,  Tae Wook Kang ,  Sung Eun Kim ,  Hyuk Kim ,  Hyung-Il Park ,  Kwang Il Oh ,  Jae-Jin Lee

    IPC: G06F1/00 ,  G06F1/10 ,  G06F15/78

    Abstract: A low power system on chip for supporting partial clock gating is provided. The system on chip includes a network on chip including a first CG-network interface module, a second CG-network interface module, and a clock gating control module, a first IP block that communicates through the first CG-network interface module, and a second IP block that communicates through the second CG-network interface module. The clock gating control module receives a clock gating request from the first IP block, outputs a communication control signal to the second CG-network interface module in response to the received clock gating request, and performs a clock gating operation for a clock signal in response to the received clock gating request to selectively deliver the clock signal to the second IP block.

    Human body communication device and operating method of the same
    7.
    发明授权
    Human body communication device and operating method of the same 有权

    公开(公告)号：US11509403B2

    公开(公告)日：2022-11-22

    申请号：US16816109

    申请日：2020-03-11

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Tae Wook Kang ,  Sung Eun Kim ,  Kwang Il Oh ,  Hyuk Kim ,  Mi Jeong Park ,  Hyung-Il Park ,  Kyung Jin Byun ,  Jae-Jin Lee ,  In Gi Lim

    IPC: H04B13/00 ,  H04B1/44

    Abstract: Provided are a human body communication device and an operating method of the same. The human body communication device according to an embodiment of the inventive concept includes a first electrode, a second electrode, a transmitting circuit, a receiving circuit, a ground electrode, and a switch. The transmitting circuit generates a first signal in a transmitting mode and transmits the first signal to the first electrode. The receiving circuit receives a second signal from the first electrode in the receiving mode. The receiving circuit includes a differential amplifier that amplifies a difference between a voltage level of a first input terminal depending on the second signal and a voltage level of a second input terminal. The switch electrically connects the second electrode and the ground electrode in the transmitting mode, and electrically connects the second electrode and the second input terminal in the receiving mode.

    Neuromorphic arithmetic device
    10.
    发明授权
    Neuromorphic arithmetic device 有权

    公开(公告)号：US10803383B2

    公开(公告)日：2020-10-13

    申请号：US15828153

    申请日：2017-11-30

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Kwang Il Oh ,  Sung Eun Kim ,  Seong Mo Park ,  Hyung-Il Park ,  Joo Hyun Lee

    IPC: G06N3/08 ,  H03K3/017 ,  G06N3/04 ,  H03K21/02 ,  G06N3/063 ,  H03K3/03

    Abstract: Provided is a neuromorphic arithmetic device. The neuromorphic arithmetic device may include a synapse circuit, a metal line having an inherent capacitance component, an oscillator, a comparator, and a capacitance calibrator. The synapse circuit may be configured to perform a multiplication operation on a PWM signal and a weight to generate a current. The metal line may include a metal line capacitor in which a charge of the current is stored. The oscillator generates a plurality of pulses on the basis of the charge stored in the metal line capacitor. The comparator may compare a frequency of the plurality of pulses and a target frequency, and may generate a control signal on the basis of a result of the comparison. The capacitance calibrator may adjust a capacitance value of the metal line capacitor on the basis of the control signal.

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