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公开(公告)号：US20240195400A1
公开(公告)日：2024-06-13
申请号：US18454507
申请日：2023-08-23
Inventor： Min-Hyung CHO , Yi-Gyeong KIM , Su-Jin PARK , Young-Deuk JEON
CPC classification number: H03K7/08 , H03K5/05 , H03K5/131 , H03K5/15066
Abstract: Disclosed herein are an apparatus and method for monitoring the duty cycle of a memory clock signal. The apparatus for monitoring a duty cycle of a memory clock signal includes a clock frequency converter configured to generate a second monitoring target clock signal by decreasing a frequency of a first monitoring target clock signal while maintaining a duty cycle of the first monitoring target clock signal, and a pulse counter configured to measure a pulse width of the second monitoring target clock signal using a reference clock signal.
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公开(公告)号：US20240163139A1
公开(公告)日：2024-05-16
申请号：US18506544
申请日：2023-11-10
Inventor： Young-deuk JEON , Young-Su KWON , Yi-Gyeong KIM , Su-Jin PARK , Min-Hyung CHO , Jae-Woong CHOI
CPC classification number: H04L25/03057 , G06F13/16 , H04L25/0272 , G06F2213/16
Abstract: Disclosed herein is an apparatus for receiving data from memory. The apparatus receives a data signal and a clock signal output from memory and includes a Decision Feedback Equalizer (DFE) including two or more differential signal path units configured to determine and output an output value corresponding to the data signal. Each of the two or more differential signal path units may determine a current output value by reflecting a previous output value fed back from a different one of the two or more differential signal path units in such a way that they operate at different clocks, and may include an offset control unit configured to adjust an offset at an input stage and a feedback control unit configured to change a load of an output stage using the previous output value fed back from the different one of the two or more differential signal path units.
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公开(公告)号：US20240195399A1
公开(公告)日：2024-06-13
申请号：US18223101
申请日：2023-07-18
Inventor： Yi-Gyeong KIM , Young-Su KWON , Su-Jin PARK , Young-Deuk JEON , Min-Hyung CHO , Jae-Woong CHOI
CPC classification number: H03K5/1565 , G06F1/12 , G11C11/4076 , H03K5/131 , H03K5/135 , H03L7/0812 , H03K2005/00058
Abstract: Disclosed herein are a duty cycle monitoring method and apparatus for a memory interface, including receiving a clock signal as input and generating a first delay time offset and a second delay time offset, receiving the clock signal and the first delay time offset and then outputting a first delayed signal, receiving the first delayed signal and the second delay time offset and then outputting a second delayed signal, receiving the clock signal and the second delayed signal and then outputting a delay value corresponding to a half-period of the clock signal, and monitoring, based on the first delayed signal, whether a duty cycle of the clock signal conforms to a duty cycle specification.
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公开(公告)号：US20240194241A1
公开(公告)日：2024-06-13
申请号：US18223097
申请日：2023-07-18
Inventor： Young-Deuk JEON , Young-Su KWON , Yi-Gyeong KIM , Su-Jin PARK , Min-Hyung CHO , Jae-Woong CHOI
IPC: G11C11/4074 , G11C11/4076
CPC classification number: G11C11/4074 , G11C11/4076
Abstract: Disclosed herein is an apparatus for adjusting a reference voltage. The apparatus may include a gate signal generation unit for generating an RDQS gate signal, a reference voltage generation unit for setting a reference voltage based on the RDQS gate signal, and a reset counter for holding a voltage at the time at which the RDQS gate signal becomes low when the RDQS gate signal is not applied to the reference voltage generation unit for a specific time period.
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