知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

79 records (took 0.023 seconds)

    PROGRAMMING METHOD OF AN ACTIVATION FUNCTION AND AN ACTIVATION FUNCTION PROGRAMMING UNIT
    1.
    发明申请
    PROGRAMMING METHOD OF AN ACTIVATION FUNCTION AND AN ACTIVATION FUNCTION PROGRAMMING UNIT 有权

    公开(公告)号：US20250148272A1

    公开(公告)日：2025-05-08

    申请号：US19007909

    申请日：2025-01-02

    Applicant: DEEPX CO., LTD.

    Inventor： Jong Hoon SHIN ,  Lok Won KIM ,  Hyung Jin CHUN ,  Ho Seung KIM

    IPC: G06N3/048

    Abstract: An activation function conversion program unit and method may be configured to approximate a target activation function to a programmed activation function through machine-learning of an artificial neural network. The method may include setting up a target activation function; approximating the target activation function to a programmed activation function by machine-learning an artificial neural network; and converting the programmed activation function into a slope and offset and storing it in a lookup table. Accordingly, the computation speed and power consumption of the programmed activation function execution unit of an NPU may be optimized.

    NPU, SOC AND ELECTRONIC DEVICE FOR CONTROLLING PEAK POWER BY DIVIDING CLOCK
    2.
    发明申请
    NPU, SOC AND ELECTRONIC DEVICE FOR CONTROLLING PEAK POWER BY DIVIDING CLOCK 有权

    公开(公告)号：US20250068586A1

    公开(公告)日：2025-02-27

    申请号：US18784455

    申请日：2024-07-25

    Applicant: DEEPX CO., LTD.

    Inventor： Lok Won KIM ,  Seong Jin LEE ,  Jin Gun SONG

    IPC: G06F15/80 ,  G06F1/08

    Abstract: A neural processing unit (NPU) is proposed. The NPU may comprise a first circuit configured to perform operations for an artificial neural network (ANN) model, and arranged for a plurality of processing elements (PE) groups including a plurality of PEs, and a second circuit configured to operate as a clock divider configured to generate a plurality of clock signals having different phases, respectively, by dividing a source clock signal and provide the plurality of clock signals to the plurality of PE groups. A first clock signal of the plurality of clock signals may be provided to a first PE group of the plurality of PE groups, and a second clock signal of the plurality of clock signals may be provided to a second PE group of the plurality of PE groups.

    SYSTEM AND SOC FOR LOWERING PEAK POWER USING VARIABLE FREQUENCY
    4.
    发明申请
    SYSTEM AND SOC FOR LOWERING PEAK POWER USING VARIABLE FREQUENCY 有权

    公开(公告)号：US20240419957A1

    公开(公告)日：2024-12-19

    申请号：US18819533

    申请日：2024-08-29

    Applicant: DEEPX CO., LTD.

    Inventor： Lok Won KIM ,  Seong Jin LEE

    IPC: G06N3/063 ,  G06F1/12

    Abstract: A system may comprise a neural processing unit (NPU) including a plurality of processing elements (PEs) capable of performing computations for at least one artificial neural network (ANN) model; and a switching circuit. The switching circuit may be configured to select one clock signal among a plurality of clock signals having different frequencies, and supply the selected clock signal to the NPU. The one clock signal may be selected based on a utilization rate of the plurality of PEs for a particular layer among a plurality of layers of the at least one ANN model.

    SOC AND SYSTEM INCLUDING TWO OR MORE NPUS BEING DISTRIBUTEDLY OPERATED IN DIFFERENT TWO PHASES
    5.
    发明申请
    SOC AND SYSTEM INCLUDING TWO OR MORE NPUS BEING DISTRIBUTEDLY OPERATED IN DIFFERENT TWO PHASES 有权

    公开(公告)号：US20240419210A1

    公开(公告)日：2024-12-19

    申请号：US18819437

    申请日：2024-08-29

    Applicant: DEEPX CO., LTD.

    Inventor： Lok Won KIM ,  Jin Gun SONG ,  Seong Jin LEE

    IPC: G06F1/08 ,  G06F15/80

    Abstract: A system-on-chip (SoC) may comprise a semi-conductor substrate; a first circuitry, disposed on the semi-conductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network model (ANN); a second circuitry, disposed on the semi-conductor substrate, provided for a second NPU configured to perform operations of an ANN model, each of the first NPU and the second NPU including a plurality of processing elements (PEs), the plurality of PEs including an adder, a multiplier, and an accumulator; and a clock signal supply circuit, disposed on the semi-conductor substrate, configured to output one or more clock signals, wherein a first clock signal among the one or more clock signals may be supplied to the first NPU, and a second clock signal among the one or more clock signals may be supplied to the second NPU.

    METHOD FOR PERFORMING AGING TEST ON SEMICONDUCTOR USED FOR NEURAL NETWORK
    6.
    发明公开
    METHOD FOR PERFORMING AGING TEST ON SEMICONDUCTOR USED FOR NEURAL NETWORK 审中-公开

    公开(公告)号：US20240274225A1

    公开(公告)日：2024-08-15

    申请号：US18648655

    申请日：2024-04-29

    Applicant: DEEPX CO., LTD.

    Inventor： Lok Won KIM

    IPC: G11C29/00 ,  G05B19/418 ,  G06F11/26 ,  G11C29/10

    CPC classification number: G11C29/78 ,  G05B19/41875 ,  G06F11/26 ,  G11C29/10 ,  G05B2219/32368 ,  G05B2219/45031

    Abstract: Provided is a method for performing an aging test on a neural processing unit (NPU) with a capability of a runtime test. The method may comprise: performing an aging test on the NPU which comprises a plurality of functional components. The plurality of functional components may comprise at least one memory and plural processing elements. The performing of the aging test may include: performing a scan test on the NPU to verify whether at least one functional component in the NPU is defective or not; and performing a memory test on the at least one memory. At least one of the scan test and the memory test may be repeatedly performed to put a stress on the NPU for the aging test. The aging test may be repeated by a predetermined number.

    IMAGE PROCESSING METHOD USING ARTIFICIAL NEURAL NETWORK, AND NEURAL PROCESSING UNIT
    8.
    发明公开
    IMAGE PROCESSING METHOD USING ARTIFICIAL NEURAL NETWORK, AND NEURAL PROCESSING UNIT 审中-公开

    公开(公告)号：US20240104912A1

    公开(公告)日：2024-03-28

    申请号：US18267095

    申请日：2022-07-01

    Applicant: DEEPX CO., LTD.

    Inventor： Lok Won KIM ,  Shin Woo JEON

    IPC: G06V10/82 ,  G06V10/70

    CPC classification number: G06V10/82 ,  G06V10/87

    Abstract: An image processing method includes receiving an image including an object; classifying at least one object in the image using a first model on the basis of an artificial neural network configured to classify the at least one object by inputting the image; and obtaining an image having improved quality according to the at least one object by inputting the image in which the at least one object is classified by using at least one model among a plurality of second models on the basis of an artificial neural network configured to output a specialized processing applied image according to a particular object by inputting the received image.

    SOC FOR OPERATING PLURAL NPUS ACCORDING TO PLURAL CLOCK SIGNALS HAVING MULTI-PHASES
    9.
    发明公开
    SOC FOR OPERATING PLURAL NPUS ACCORDING TO PLURAL CLOCK SIGNALS HAVING MULTI-PHASES 审中-公开

    公开(公告)号：US20240012445A1

    公开(公告)日：2024-01-11

    申请号：US18473746

    申请日：2023-09-25

    Applicant: DEEPX CO., LTD.

    Inventor： Lok Won KIM ,  Jin Gun SONG ,  Seong Jin LEE

    IPC: G06F1/08 ,  G06F15/80

    CPC classification number: G06F1/08 ,  G06F15/80

    Abstract: A system-on-chip (SoC) may comprise a semi-conductor substrate; a first circuitry, disposed on the semi-conductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network model (ANN); a second circuitry, disposed on the semi-conductor substrate, provided for a second NPU configured to perform operations of an ANN model, each of the first NPU and the second NPU including a plurality of processing elements (PEs), the plurality of PEs including an adder, a multiplier, and an accumulator; and a clock signal supply circuit, disposed on the semi-conductor substrate, configured to output one or more clock signals, wherein a first clock signal among the one or more clock signals may be supplied to the first NPU, and a second clock signal among the one or more clock signals may be supplied to the second NPU.

    NEURAL PROCESSING UNIT CAPABLE OF SWITCHING ANN MODELS
    10.
    发明公开
    NEURAL PROCESSING UNIT CAPABLE OF SWITCHING ANN MODELS 审中-公开

    公开(公告)号：US20230316040A1

    公开(公告)日：2023-10-05

    申请号：US18312660

    申请日：2023-05-05

    Applicant: DEEPX CO., LTD.

    Inventor： You Jun KIM ,  Ha Joon YU ,  Lok Won KIM

    IPC: G06N3/04

    CPC classification number: G06N3/04

    Abstract: A neural processing unit (NPU) mounted on a movable device for detecting object is provided. The NPU may comprise a plurality of processing elements (PEs), configured to process an operation of a first artificial neural network model (ANN) and an operation of a second ANN different from the first ANN; a memory configured to store a portion of a data of the first ANN and the second ANN; and a controller configured to control the PEs and the memory to selectively perform a convolution operation of the first ANN or the second ANN based on a determination data, wherein the determination data may include an object detection performance data of the first ANN and the second ANN, respectively.

Patent Agency Ranking