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    TECHNOLOGY FOR CONTROLLING PEAK POWER BY DIVIDING CLOCK
    1.
    发明公开
    TECHNOLOGY FOR CONTROLLING PEAK POWER BY DIVIDING CLOCK 审中-公开

    公开(公告)号：US20240211431A1

    公开(公告)日：2024-06-27

    申请号：US18601598

    申请日：2024-03-11

    Applicant: DEEPX CO., LTD.

    Inventor： Lok Won KIM ,  Seong Jin LEE ,  Jin Gun SONG

    IPC: G06F15/80 ,  G06F1/08

    CPC classification number: G06F15/80 ,  G06F1/08

    Abstract: A neural processing unit (NPU) is proposed. The NPU may comprise a first circuit configured to perform operations for an artificial neural network (ANN) model, and arranged for a plurality of processing elements (PE) groups including a plurality of PEs, and a second circuit configured to operate as a clock divider configured to generate a plurality of clock signals having different phases, respectively, by dividing a source clock signal and provide the plurality of clock signals to the plurality of PE groups. A first clock signal of the plurality of clock signals may be provided to a first PE group of the plurality of PE groups, and a second clock signal of the plurality of clock signals may be provided to a second PE group of the plurality of PE groups.

    SYSTEM-ON-CHIP FOR ARTIFICIAL NEURAL NETWORK BEING OPERATED ACCORDING TO DYNAMICALLY CALIBRATED PHASE OF CLOCK SIGNAL
    2.
    发明公开
    SYSTEM-ON-CHIP FOR ARTIFICIAL NEURAL NETWORK BEING OPERATED ACCORDING TO DYNAMICALLY CALIBRATED PHASE OF CLOCK SIGNAL 审中-公开

    公开(公告)号：US20240013039A1

    公开(公告)日：2024-01-11

    申请号：US18473777

    申请日：2023-09-25

    Applicant: DEEPX CO., LTD.

    Inventor： Seong Jin LEE ,  Jin Gun SONG ,  Lok Won KIM

    IPC: G06N3/063

    CPC classification number: G06N3/063

    Abstract: A system-on-chip (SoC) may comprise a semiconductor substrate; a first circuitry, disposed on the semiconductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network (ANN) model; a second circuitry, disposed on the semiconductor substrate, provided for a second NPU configured to perform operations of an ANN model; and a third circuitry, disposed on the semiconductor substrate, configured to generate a control signal to selectively output one or more clock signals, wherein each of the first NPU and the second NPU may include a plurality of processing elements (PEs), and the plurality of PEs may include an adder, a multiplier, and an accumulator, and wherein the one or more clock signals may include an original clock signal and one or more phase-delayed clock signals based on a phase of the original clock signal.

    NPU AND SOC BEING OPERATED BASED ON TWO OR MORE DIFFERENT CLOCK SIGNALS
    3.
    发明申请
    NPU AND SOC BEING OPERATED BASED ON TWO OR MORE DIFFERENT CLOCK SIGNALS 有权

    公开(公告)号：US20250045574A1

    公开(公告)日：2025-02-06

    申请号：US18595047

    申请日：2024-03-04

    Applicant: DEEPX CO., LTD.

    Inventor： Seong Jin LEE ,  Jung Boo PARK ,  Lok Won KIM

    IPC: G06N3/063

    Abstract: A neural processing unit may comprise a first circuitry including a plurality of processing elements (PEs) configured to perform operations of an artificial neural network model, the plurality of PEs including an adder, a multiplier, and an accumulator, and a clock signal supply circuitry configured to output one or more clock signals. When the plurality of PEs include a first group of PEs and a second group of PEs, a first clock signal among the one or more clock signals, may be supplied to the first group of PEs and a second clock signal among the one or more clock signals, may be supplied to the second group of PEs. At least one of the first and second clock signals may have a preset phase based on a phase of an original clock signal.

    Soc and system operated based on clock signals having different phases
    4.
    发明公开
    Soc and system operated based on clock signals having different phases 审中-公开

    公开(公告)号：US20240211741A1

    公开(公告)日：2024-06-27

    申请号：US18594928

    申请日：2024-03-04

    Applicant: DEEPX CO., LTD.

    Inventor： Seong Jin LEE ,  Jin Gun SONG ,  Lok Won KIM

    IPC: G06N3/063

    CPC classification number: G06N3/063

    Abstract: A system-on-chip (SoC) may comprise a semiconductor substrate; a first circuitry, disposed on the semiconductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network (ANN) model; a second circuitry, disposed on the semiconductor substrate, provided for a second NPU configured to perform operations of an ANN model; and a third circuitry, disposed on the semiconductor substrate, configured to generate a control signal to selectively output one or more clock signals, wherein each of the first NPU and the second NPU may include a plurality of processing elements (PEs), and the plurality of PEs may include an adder, a multiplier, and an accumulator, and wherein the one or more clock signals may include an original clock signal and one or more phase-delayed clock signals based on a phase of the original clock signal.

    NPU, SOC AND ELECTRONIC DEVICE BEING OPERATED BASED ON DYNAMICALLY CALIBRATED PHASE OF CLOCK SIGNAL
    5.
    发明申请
    NPU, SOC AND ELECTRONIC DEVICE BEING OPERATED BASED ON DYNAMICALLY CALIBRATED PHASE OF CLOCK SIGNAL 有权

    公开(公告)号：US20250124268A1

    公开(公告)日：2025-04-17

    申请号：US18776305

    申请日：2024-07-18

    Applicant: DEEPX CO., LTD.

    Inventor： Lok Won KIM ,  Seong Jin LEE ,  Jung Boo PARK

    IPC: G06N3/063 ,  G06F1/06 ,  G06N3/0464

    Abstract: A neural processing unit may comprise a first circuit configured to perform operations for an artificial neural network (ANN) model, and arranged for a plurality of groups of processing elements (PEs) including a plurality of PEs; a second circuit arranged to output a plurality of clock signals to the first circuit; a third circuit configured to measure a ratio of peak power and average power of at least the first circuit; and a fourth circuit, arranged to dynamically calibrate a phase of at least one of the plurality of clock signals of the second circuit based on the ratio of peak power and average power measured in the third circuit.

    TECHNOLOGY FOR LOWERING INSTANTANEOUS POWER CONSUMPTION OF NEURAL PROCESSING UNIT
    6.
    发明申请
    TECHNOLOGY FOR LOWERING INSTANTANEOUS POWER CONSUMPTION OF NEURAL PROCESSING UNIT 有权

    公开(公告)号：US20240378431A1

    公开(公告)日：2024-11-14

    申请号：US18479161

    申请日：2023-10-02

    Applicant: DEEPX CO., LTD.

    Inventor： Lok Won KIM ,  Jung Boo PARK ,  Seong Jin LEE

    IPC: G06N3/063

    Abstract: A system may comprise a neural processing unit (NPU) including at least one memory and a plurality of processing elements (PEs) capable of performing operations for at least one artificial neural network (ANN) model. The plurality of PEs may include an adder, a multiplier, and an accumulator. The plurality of PEs may include a first group of PEs configured to operate on a first portion of a clock signal and a second group of PEs configured to operate on a second portion of the clock signal.

    TECHNOLOGY FOR LOWERING INSTANTANEOUS POWER CONSUMPTION OF NEURAL PROCESSING UNIT
    7.
    发明公开
    TECHNOLOGY FOR LOWERING INSTANTANEOUS POWER CONSUMPTION OF NEURAL PROCESSING UNIT 审中-公开

    公开(公告)号：US20230359877A1

    公开(公告)日：2023-11-09

    申请号：US18353404

    申请日：2023-07-17

    Applicant: DEEPX CO., LTD.

    Inventor： Lok Won KIM ,  Jung Boo PARK ,  Seong Jin LEE

    IPC: G06N3/063

    CPC classification number: G06N3/063

    Abstract: A system may comprise a neural processing unit (NPU) including at least one memory and a plurality of processing elements (PEs) capable of performing operations for at least one artificial neural network (ANN) model. The plurality of PEs may include an adder, a multiplier, and an accumulator. The plurality of PEs may include a first group of PEs configured to operate on a first portion of a clock signal and a second group of PEs configured to operate on a second portion of the clock signal.

    NPU, SOC AND ELECTRONIC DEVICE FOR CONTROLLING PEAK POWER BY DIVIDING CLOCK
    8.
    发明申请
    NPU, SOC AND ELECTRONIC DEVICE FOR CONTROLLING PEAK POWER BY DIVIDING CLOCK 有权

    公开(公告)号：US20250068586A1

    公开(公告)日：2025-02-27

    申请号：US18784455

    申请日：2024-07-25

    Applicant: DEEPX CO., LTD.

    Inventor： Lok Won KIM ,  Seong Jin LEE ,  Jin Gun SONG

    IPC: G06F15/80 ,  G06F1/08

    Abstract: A neural processing unit (NPU) is proposed. The NPU may comprise a first circuit configured to perform operations for an artificial neural network (ANN) model, and arranged for a plurality of processing elements (PE) groups including a plurality of PEs, and a second circuit configured to operate as a clock divider configured to generate a plurality of clock signals having different phases, respectively, by dividing a source clock signal and provide the plurality of clock signals to the plurality of PE groups. A first clock signal of the plurality of clock signals may be provided to a first PE group of the plurality of PE groups, and a second clock signal of the plurality of clock signals may be provided to a second PE group of the plurality of PE groups.

    SYSTEM AND SOC FOR LOWERING PEAK POWER USING VARIABLE FREQUENCY
    9.
    发明申请
    SYSTEM AND SOC FOR LOWERING PEAK POWER USING VARIABLE FREQUENCY 有权

    公开(公告)号：US20240419957A1

    公开(公告)日：2024-12-19

    申请号：US18819533

    申请日：2024-08-29

    Applicant: DEEPX CO., LTD.

    Inventor： Lok Won KIM ,  Seong Jin LEE

    IPC: G06N3/063 ,  G06F1/12

    Abstract: A system may comprise a neural processing unit (NPU) including a plurality of processing elements (PEs) capable of performing computations for at least one artificial neural network (ANN) model; and a switching circuit. The switching circuit may be configured to select one clock signal among a plurality of clock signals having different frequencies, and supply the selected clock signal to the NPU. The one clock signal may be selected based on a utilization rate of the plurality of PEs for a particular layer among a plurality of layers of the at least one ANN model.

    SOC AND SYSTEM INCLUDING TWO OR MORE NPUS BEING DISTRIBUTEDLY OPERATED IN DIFFERENT TWO PHASES
    10.
    发明申请
    SOC AND SYSTEM INCLUDING TWO OR MORE NPUS BEING DISTRIBUTEDLY OPERATED IN DIFFERENT TWO PHASES 有权

    公开(公告)号：US20240419210A1

    公开(公告)日：2024-12-19

    申请号：US18819437

    申请日：2024-08-29

    Applicant: DEEPX CO., LTD.

    Inventor： Lok Won KIM ,  Jin Gun SONG ,  Seong Jin LEE

    IPC: G06F1/08 ,  G06F15/80

    Abstract: A system-on-chip (SoC) may comprise a semi-conductor substrate; a first circuitry, disposed on the semi-conductor substrate, provided for a first neural processing unit (NPU) configured to perform operations of an artificial neural network model (ANN); a second circuitry, disposed on the semi-conductor substrate, provided for a second NPU configured to perform operations of an ANN model, each of the first NPU and the second NPU including a plurality of processing elements (PEs), the plurality of PEs including an adder, a multiplier, and an accumulator; and a clock signal supply circuit, disposed on the semi-conductor substrate, configured to output one or more clock signals, wherein a first clock signal among the one or more clock signals may be supplied to the first NPU, and a second clock signal among the one or more clock signals may be supplied to the second NPU.

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