公开(公告)号：US5962867A

公开(公告)日：1999-10-05

申请号：US990418

申请日：1997-12-15

Applicant: Chwen-Ming Liu

Inventor： Chwen-Ming Liu

IPC: G01R31/307 ,  H01L23/544 ,  H01L23/58 ,  H01L23/48

CPC classification number: H01L22/34 ,  G01R31/307

Abstract: The inspection and measurement of critical dimensions of patterned features during the manufacture of sub-micron integrated circuits relies heavily upon the scanning-electron-microscope(SEM). This instrument is capable of quick, clean, and accurate measurements of features on large in-process silicon wafers. However, such features are frequently isolated from the electrical ground of the microscope by virtue of their circuit design. This creates a charge build up from the electron beam in the SEM and causes distorted and indistinct images, incapable of being measured. Also, such static charge build-up can be destructive to certain circuit elements. This invention teaches the use of independent inspection test structures, fabricated in wafer saw kerf regions or within designated test sites, especially designed to provide a reduction or elimination of charge build up during SEM observation. The structures are built to follow conventional processing and carry the desired features to be examined at each successive process level. They are particularly useful for examining and measuring contact and via openings, and measuring interconnection metal line widths and spacings, including polysilicon structures.

Abstract translation: 在亚微米集成电路制造期间，图案特征的关键尺寸的检查和测量主要依赖于扫描电子显微镜（SEM）。 该仪器能够快速，清洁和精确测量大型在线硅片的特征。 然而，由于它们的电路设计，这些特征经常与显微镜的电接地隔离。 这产生了从SEM中的电子束积累的电荷，并导致失真和不清晰的图像，不能被测量。 此外，这种静电荷积聚可能对某些电路元件具有破坏性。 本发明教导了使用独立的检查测试结构，其制造在晶片锯切区域或指定的测试位置内，特别设计用于在扫描电镜观察期间减少或消除电荷累积。 这些结构被构建为遵循常规处理并且携带在每个连续过程级别要检查的期望特征。 它们特别适用于检测和测量接触和通孔，以及测量互连金属线宽度和间距，包括多晶硅结构。

公开(公告)号：US5834346A

公开(公告)日：1998-11-10

申请号：US949351

申请日：1997-10-14

Applicant: Yi-Lin Sun ,  Cheng-Yeh Shih ,  Chwen-Ming Liu

Inventor： Yi-Lin Sun ,  Cheng-Yeh Shih ,  Chwen-Ming Liu

IPC: H01L21/3105 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/302 ,  H01L21/336

CPC classification number: H01L21/3105 ,  H01L21/76801

Abstract: A method for preventing bubble formation over source/drain active areas in p-channel MOSFETs is described. Bubble formation occurs when the source/drain areas and silicon containing gate electrodes are implanted with BF.sub.2.sup.+ molecule ions following an anisotropic LDD spacer etch using a plasma. It is found that the plasma causes the silicon surface to become prone to adsorption of BF.sub.2.sup.+ molecule ions during the source/drain/gate implantation. These adsorbed species are released and form bubbles during reflow of a subsequently deposited glass layer. The invention performs the spacer etch only partially with the anisotropic plasma and completes the spacer formation with a wet etch. The active silicon and gate electrode surfaces are thus not damaged by the plasma. Consequently adsorption of BF.sub.2.sup.+ molecule ions is inhibited and bubble formation does not occur during reflow.

Abstract translation: 描述了一种用于防止在p沟道MOSFET中的源极/漏极有源区上形成气泡的方法。 当使用等离子体进行各向异性LDD间隔物蚀刻之后，在源极/漏极区域和含硅栅电极注入BF 2 +分子离子时发生气泡形成。 发现等离子体在源极/漏极/栅极注入期间使硅表面易于吸附BF 2+分子离子。 这些吸附的物质在随后沉积的玻璃层的回流期间被释放并形成气泡。 本发明仅用各向异性等离子体部分地进行间隔物蚀刻，并用湿蚀刻完成间隔物的形成。 因此，活性硅和栅电极表面不被等离子体损坏。 因此，BF2 +分子离子的吸附被抑制，并且在回流期间不会发生气泡形成。

公开(公告)号：US5757053A

公开(公告)日：1998-05-26

申请号：US595609

申请日：1996-04-19

Applicant: Chwen-Ming Liu

Inventor： Chwen-Ming Liu

IPC: H01L21/02 ,  H01L21/8244 ,  H01L27/11 ,  H01L27/02 ,  H01L29/76

CPC classification number: H01L28/20 ,  H01L27/11 ,  H01L27/1112 ,  Y10S148/136 ,  Y10S257/904

Abstract: A device and a method of manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises forming a first polycrystalline silicon containing layer on the semiconductor substrate, patterning and etching the first polycrystalline silicon containing layer to form steps on either side thereof, forming a dielectric layer over the first polycrystalline silicon containing layer with the steps on either side of the first polycrystalline silicon containing layer, forming a blanket of a second polycrystalline silicon containing layer extending over the interpolysilicon layer, and ion implanting the second polycrystalline silicon containing layer in a blanket implant of a light dose of dopant including ion implanting resistive regions with far higher resistivity in the regions over the steps.

Abstract translation: 在包括具有电阻器的SRAM单元的半导体衬底上制造半导体器件的器件和方法包括在半导体衬底上形成第一多晶硅层，对第一多晶硅含量层进行图案化和蚀刻以在两侧形成步骤 在所述第一多晶硅含硅层上形成电介质层，所述第一多晶硅含有层的任一侧上具有台阶，形成在所述多晶硅层上延伸的第二多晶硅含量层的覆盖层，以及离子注入所述第二多晶硅 包含光剂量的掺杂剂的包覆层植入物，其包括在步骤上的区域中具有远高于电阻率的离子注入电阻区域。

公开(公告)号：US5393682A

公开(公告)日：1995-02-28

申请号：US165349

申请日：1993-12-13

Applicant: Chwen-Ming Liu

Inventor： Chwen-Ming Liu

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/423 ,  H01L21/265

CPC classification number: H01L29/66765 ,  H01L21/28008 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/42384 ,  Y10S148/127 ,  Y10S148/161

Abstract: A new method of forming a tapered polysilicon etching profile in the manufacture of a thin film transistor integrated circuit is described. A layer of polysilicon is deposited over the surface of a semiconductor substrate. Ions are implanted into the polysilicon layer whereby the upper half of the polysilicon layer is damaged by the presence of the ions within the layer. The polysilicon layer is anisotropically etched. The polysilicon layer is isotropically etched whereby the damaged upper portion of the layer is etched faster than is the undamaged lower portion resulting in a tapered polysilicon layer. A layer of gate oxide is deposited over the surface of the tapered polysilicon layer. Then the thin film transistor body is formed. A layer of amorphous silicon is deposited over the surface of the gate oxide layer. The amorphous silicon layer is recrystallized to yield larger grain sizes. Channel and source/drain regions are formed within the recrystallized amorphous silicon layer to complete formation of the thin film transistor body. An insulating layer is deposited over the thin film transistor body and the silicon substrate. Contact openings are made through the insulating layer to the source/drain regions and filled with a conductive material to complete the contacts completing the formation of the thin film transistor integrated circuit.

Abstract translation: 描述了在薄膜晶体管集成电路的制造中形成锥形多晶硅蚀刻轮廓的新方法。 在半导体衬底的表面上沉积多晶硅层。 离子被注入到多晶硅层中，由此多晶硅层的上半部分被层内的离子的存在所损坏。 多晶硅层被各向异性蚀刻。 多晶硅层被各向同性地蚀刻，由此损坏的上部被蚀刻得比未损坏的下部更快地蚀刻，从而形成锥形多晶硅层。 栅极氧化物层沉积在锥形多晶硅层的表面上。 然后形成薄膜晶体管体。 在栅极氧化物层的表面上沉积非晶硅层。 非晶硅层重结晶以产生较大的晶粒尺寸。 在再结晶的非晶硅层内形成沟道和源极/漏极区，以完成薄膜晶体管体的形成。 绝缘层沉积在薄膜晶体管体和硅衬底上。 通过绝缘层到源极/漏极区域形成接触开口，并填充导电材料，以完成完成薄膜晶体管集成电路形成的触点。

公开(公告)号：US06314379B1

公开(公告)日：2001-11-06

申请号：US08984882

申请日：1997-12-04

Applicant: Ding-Dar Hu ,  Chwen-Ming Liu ,  Chih-Ming Huang ,  Li-Chun Chen

Inventor： Ding-Dar Hu ,  Chwen-Ming Liu ,  Chih-Ming Huang ,  Li-Chun Chen

IPC: G06F1900

CPC classification number: H01L22/20 ,  G01R31/2894

Abstract: An integrated defect yield management and query system for a semiconductor wafer fabrication process is disclosed. A local area network connects various testing devices for testing defect conditions of wafers, a defect yield management server and a client device. After inspection, these devices generate a plurality of process records corresponding to each of the semiconductor wafers. The defect yield management server retrieves the process records through the local area network. These process records are stored in a database divided into a plurality of fields, wherein each field corresponds to a specific defect property of the semiconductor wafers. Therefore, these acquired on-line data and their related history records can be accessed by using an inquiring interface, and the client device can effectively poll the process records stored in the database of the defect yield management server.

Abstract translation: 公开了一种用于半导体晶片制造工艺的综合缺陷产量管理和查询系统。 局域网连接各种测试设备，用于测试晶片的缺陷状况，缺陷产量管理服务器和客户端设备。 在检查之后，这些装置产生对应于每个半导体晶片的多个处理记录。 缺陷产出管理服务器通过局域网检索进程记录。 这些处理记录被存储在分成多个场的数据库中，其中每个场对应于半导体晶片的特定缺陷特性。 因此，这些获取的在线数据及其相关历史记录可以通过使用查询界面来访问，并且客户端设备可以有效地轮询存储在缺陷产量管理服务器的数据库中的过程记录。

公开(公告)号：US06248624B1

公开(公告)日：2001-06-19

申请号：US08918121

申请日：1997-08-27

Applicant: Chwen-Ming Liu

Inventor： Chwen-Ming Liu

IPC: H01L218242

CPC classification number: H01L28/87 ,  H01L21/31116 ,  H01L27/10855

Abstract: The present invention discloses a method for forming a fin-type DRAM stacked capacitor that has improved charge capacity by first depositing multiple layers of different insulating materials on a preprocessed semiconductor substrate, then dry etching a contact opening through the multiple layers of insulating materials to form a node contact on the substrate, and then wet etching the contact opening in an etchant that has different etch rates for the different insulating materials exposed in the contact opening such that a zig-zag configuration in the contact opening is formed for producing a capacitor has increased surface area and therefore increased charge capacity. Suitable insulating layers utilized are doped oxide layers and non-doped oxide layers which can be etched at different etch rates when an etchant of SC1 is used.

Abstract translation: 本发明公开了一种通过在预处理的半导体衬底上首先沉积多层不同绝缘材料，然后通过多层绝缘材料干蚀刻接触开口形成具有改善电荷容量的翅片式DRAM叠层电容器的方法，以形成 在衬底上的节点接触，然后在对接触开口中暴露的不同绝缘材料具有不同蚀刻速率的蚀刻剂中湿式蚀刻接触开口，使得形成用于制造电容器的接触开口中的之字形配置 增加表面积，从而增加充电容量。 使用的合适的绝缘层是掺杂氧化物层和非掺杂氧化物层，当使用SC1的蚀刻剂时，可以以不同的蚀刻速率蚀刻。

公开(公告)号：US6005277A

公开(公告)日：1999-12-21

申请号：US157512

申请日：1998-09-21

Applicant: Chwen-Ming Liu ,  Jiann-Jong Wang ,  Chung-Chieh Liu

Inventor： Chwen-Ming Liu ,  Jiann-Jong Wang ,  Chung-Chieh Liu

IPC: H01L23/532 ,  H01L31/0232 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/53223 ,  H01L2924/0002

Abstract: A method for forming an anti-reflective-coating(ARC) layer is described. This ARC layer performs not only in its capacity to reduce reflections from its subjacent metal layer during the metal patterning photoresist exposure, but also serves as an effective etch inhibitor during subsequent via etching. Of particular importance is the ability provided by this ARC layer to sustain its etch resistance during considerable over etching such as is required when vias of different depths are to be opened. The ARC layer differs from the conventional titanium nitride ARC layer in that it has a base layer of titanium below the titanium nitride portion. It is this titanium layer and an optional intermediate Ti rich layer that sustains the over etch. Additionally, the titanium forms an improved bonding with the metal beneath providing reduced via contact resistance and greater via stability and consistency.

Abstract translation: 描述了形成抗反射涂层（ARC）层的方法。 该ARC层不仅能够在金属图案化光致抗蚀剂曝光期间从其下面的金属层减少反射的能力，而且还可以在随后的通孔蚀刻期间用作有效的蚀刻抑制剂。 特别重要的是由ARC层提供的能力，以在相当大的过蚀刻期间维持其耐蚀刻性，例如当不同深度的通孔打开时所需要的。 ARC层与常规氮化钛ARC层的不同之处在于其在钛氮化物部分下方具有钛的基底层。 正是这种钛层和可选的中间Ti富层保持了过蚀刻。 此外，钛与金属之间形成改进的粘合，提供降低的通孔接触电阻和更大的通孔稳定性和一致性。

公开(公告)号：US5736863A

公开(公告)日：1998-04-07

申请号：US666161

申请日：1996-06-19

Applicant: Chwen-Ming Liu

Inventor： Chwen-Ming Liu

IPC: G01R31/307 ,  H01L23/544 ,  H01L23/58 ,  G01R31/26

CPC classification number: H01L22/34 ,  G01R31/307

Abstract: The inspection and measurement of critical dimensions of patterned features during the manufacture of sub-micron integrated circuits relies heavily upon the scanning-electron-microscope(SEM). This instrument is capable of quick, clean, and accurate measurements of features on large in-process silicon wafers. However, such features are frequently isolated from the electrical ground of the microscope by virtue of their circuit design. This creates a charge build up from the electron beam in the SEM and causes distorted and indistinct images, incapable of being measured. Also, such static charge build-up can be destructive to certain circuit elements. This invention teaches the use of independent inspection test structures, fabricated in wafer saw kerf regions or within designated test sites, especially designed to provide a reduction or elimination of charge build up during SEM observation. The structures are built to follow conventional processing and carry the desired features to be examined at each successive process level. They are particularly useful for examining and measuring contact and via openings, and measuring interconnection metal line widths and spacings, including polysilicon structures.

公开(公告)号：US5646057A

公开(公告)日：1997-07-08

申请号：US524153

申请日：1995-09-01

Applicant: Chwen-Ming Liu ,  Jenn-Ming Huang ,  Hsien-Wei Chin ,  Huan-Chung You ,  Jang-Cheng Hsieh

Inventor： Chwen-Ming Liu ,  Jenn-Ming Huang ,  Hsien-Wei Chin ,  Huan-Chung You ,  Jang-Cheng Hsieh

IPC: H01L21/28 ,  H01L21/8234

CPC classification number: H01L21/28176 ,  H01L21/8234 ,  Y10S148/003 ,  Y10S438/91

Abstract: A method is provided for improving the performance characteristics of the MOS devices contained within an integrated circuit that has been subjected to a rapid thermal anneal. After the rapid thermal anneal the integrated circuit is heated for more than about 30 minutes at a temperature of more than about 430.degree. C. in a gaseous atmosphere that contains hydrogen, typically forming gas.

Abstract translation: 提供了一种用于改善包含在经受快速热退火的集成电路中的MOS器件的性能特性的方法。 在快速热退火之后，在含有氢的气体气氛（通常形成气体）中，在大于约430℃的温度下将集成电路加热超过约30分钟。

公开(公告)号：US5514617A

公开(公告)日：1996-05-07

申请号：US266504

申请日：1994-06-27

Applicant: Chwen-Ming Liu

Inventor： Chwen-Ming Liu

IPC: H01L21/02 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/70 ,  H01L27/00

CPC classification number: H01L28/20 ,  H01L27/11 ,  H01L27/1112 ,  Y10S148/136 ,  Y10S257/904

Abstract: A device and a method of manufacture of a semiconductor device on a semiconductor substrate including an SRAM cell with a resistor comprises forming a first polycrystalline silicon containing layer on the semiconductor substrate, patterning and etching the first polycrystalline silicon containing layer to form steps on either side thereof, forming a dielectric layer over the first polycrystalline silicon containing layer with the steps on either side of the first polycrystalline silicon containing layer, forming a blanket of a second polycrystalline silicon containing layer extending over the interpolysilicon layer, and ion implanting the second polycrystalline silicon containing layer in a blanket implant of a light dose of dopant including ion implanting resistive regions with far higher resistivity in the regions over the steps.

Abstract translation: 在包括具有电阻器的SRAM单元的半导体衬底上制造半导体器件的器件和方法包括在半导体衬底上形成第一多晶硅层，对第一多晶硅含量层进行图案化和蚀刻以在两侧形成步骤 在所述第一多晶硅含硅层上形成电介质层，所述第一多晶硅含有层的任一侧上具有台阶，形成在所述多晶硅层上延伸的第二多晶硅含量层的覆盖层，以及离子注入所述第二多晶硅 包含光剂量的掺杂剂的包覆层植入物，其包括在步骤上的区域中具有远高于电阻率的离子注入电阻区域。