公开(公告)号：US20240194161A1

公开(公告)日：2024-06-13

申请号：US17908359

申请日：2021-08-31

Applicant: BOE Technology Group Co., Ltd.

Inventor： Lizhong Wang ,  Guangcai Yuan ,  Ce Ning ,  Hehe Hu ,  Nianqi Yao ,  Xin Xie ,  Yifang Huang ,  Liping Lei ,  Chen Xu

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0286

Abstract: A display substrate and a display panel are provided, the display substrate includes a first gate driver circuit and a second gate driver circuit that are respectively arranged on a first side and a second side of a display region; the first gate driver circuit includes a plurality of first shift register units arranged in a first direction, each first shift register unit includes a first thin film transistor; the second gate driver circuit includes a plurality of second shift register units arranged in the first direction, each second shift register unit includes a second thin film transistor having the same function as the first thin film transistor; an average turn-on current of at least one first thin film transistor is Ion1, and an average turn-on current of at least one second thin film transistor is Ion2, Ion1>Ion2.

公开(公告)号：US20240162247A1

公开(公告)日：2024-05-16

申请号：US17772761

申请日：2021-06-29

Applicant: BOE Technology Group Co., Ltd.

Inventor： Fuqiang Li ,  Zhen Zhang ,  Zhenyu Zhang ,  Lizhong Wang ,  Ce Ning ,  Yunping Di ,  Zheng Fang ,  Jiahui Han ,  Chenyang Zhang ,  Yawei Wang ,  Chengfu Xu

IPC: H01L27/12

CPC classification number: H01L27/1248 ,  H01L27/1288 ,  H01L27/1222

Abstract: Disclosed are a thin film transistor and a manufacturing method therefor, a displaying base plate and a displaying apparatus. The thin film transistor includes an active layer, a first insulating layer and a gate layer which are disposed in stack, wherein the active layer includes a source contact area, a drain contact area, and a channel area connecting the source contact area and the drain contact area; the channel area includes a first channel area, a first resistance area and a second channel area sequentially disposed in a first direction; the gate layer includes a first gate and a second gate which are separately disposed; an orthographic projection of the first gate on a plane where the active layer is located covers the first channel area; and an orthographic projection of the second gate on a plane where the active layer is located covers the second channel area.

公开(公告)号：US20240103328A1

公开(公告)日：2024-03-28

申请号：US17765769

申请日：2021-06-29

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zhen Zhang ,  Fuqiang Li ,  Zhenyu Zhang ,  Yunping Di ,  Lizhong Wang ,  Zheng Fang ,  Jiahui Han ,  Yawei Wang ,  Chenyang Zhang ,  Chengfu Xu ,  Ce Ning ,  Pengxia Liang ,  Feihu Zhou ,  Xianqin Meng ,  Weiting Peng ,  Qiuli Wang ,  Binbin Tong ,  Rui Huang ,  Tianmin Zhou ,  Wei Yang

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L27/12

CPC classification number: G02F1/1368 ,  G02F1/136286 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259

Abstract: A displaying base plate and a manufacturing method thereof, and a displaying device. The displaying base plate includes a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer includes a first electrode pattern; a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate, wherein the second electrode layer is disposed closer to the substrate, the second electrode layer is connected to the first electrode pattern and the third electrode layer.

公开(公告)号：US11217697B2

公开(公告)日：2022-01-04

申请号：US16615358

申请日：2018-04-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lizhong Wang ,  Tianmin Zhou ,  Yu Wen

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L29/10 ,  H01L29/167

Abstract: An active layer of the thin-film transistor includes a channel region, a source region and a drain region. The source region and the drain region are respectively arranged on both sides of the channel region, and the channel region includes a polycrystalline silicon structure doped with a fifth group element. A potential difference between the source-drain region and the channel region is increased by doping with the fifth group element.

公开(公告)号：US20210050469A1

公开(公告)日：2021-02-18

申请号：US16812764

申请日：2020-03-09

Applicant: BOE Technology Group Co.,Ltd.

Inventor： Tianmin Zhou ,  Rui Huang ,  Lizhong Wang ,  Jipeng Song ,  Tao Yang ,  Zhaohui Qiang

IPC: H01L31/11 ,  H01L31/0224 ,  H01L31/0236 ,  H01L31/0392

Abstract: A photosensitive device, a manufacturing method thereof, a detection substrate and an array substrate are provided. The photosensitive device is formed on a substrate, and it includes a photosensitive element and a thin film transistor. The photosensitive element includes a first electrode layer on the substrate; a second electrode layer on a side of the first electrode layer distal to the substrate; and a photoelectric conversion layer between the first electrode layer and the second electrode layer. The thin film transistor is electrically connected to the photosensitive element, and it includes a first gate electrode on the substrate; an active layer on a side of the first gate electrode distal to the substrate; and a second gate electrode on a side of the active layer distal to the substrate. The first electrode layer and the second gate electrode are located in the same layer.

公开(公告)号：US10748938B2

公开(公告)日：2020-08-18

申请号：US16134201

申请日：2018-09-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Tianmin Zhou ,  Wei Yang ,  Lizhong Wang ,  Jipeng Song

IPC: H01L21/00 ,  H01L27/12 ,  H01L21/30 ,  H01L29/786

Abstract: an array substrate, a method of manufacturing the array substrate, and a display device are provided. The array substrate includes: a base substrate; a first thin film transistor and a second thin film transistor on the base substrate, wherein the first thin film transistor comprises a first active layer, the second thin film transistor comprises a second active layer, and the second active layer is on a side of the first active layer away from the base substrate; and an interlayer dielectric layer and a first buffer layer between the first active layer and the second active layer, wherein the interlayer dielectric layer is capable of supplying hydrogen and the first buffer layer is capable of blocking hydrogen.

公开(公告)号：US20200176612A1

公开(公告)日：2020-06-04

申请号：US16615358

申请日：2018-04-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lizhong Wang ,  Tianmin Zhou ,  Yu Wen

IPC: H01L29/786 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L29/167

Abstract: An active layer of the thin-film transistor includes a channel region, a source region and a drain region. The source region and the drain region are respectively arranged on both sides of the channel region, and the channel region includes a polycrystalline silicon structure doped with a fifth group element. A potential difference between the source-drain region and the channel region is increased by doping with the fifth group element.

公开(公告)号：US12235557B2

公开(公告)日：2025-02-25

申请号：US17765769

申请日：2021-06-29

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zhen Zhang ,  Fuqiang Li ,  Zhenyu Zhang ,  Yunping Di ,  Lizhong Wang ,  Zheng Fang ,  Jiahui Han ,  Yawei Wang ,  Chenyang Zhang ,  Chengfu Xu ,  Ce Ning ,  Pengxia Liang ,  Feihu Zhou ,  Xianqin Meng ,  Weiting Peng ,  Qiuli Wang ,  Binbin Tong ,  Rui Huang ,  Tianmin Zhou ,  Wei Yang

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L27/12

Abstract: A displaying base plate and a manufacturing method thereof, and a displaying device. The displaying base plate includes a substrate, and a first electrode layer disposed on one side of the substrate, wherein the first electrode layer includes a first electrode pattern; a first planarization layer disposed on one side of the first electrode layer that is away from the substrate, wherein the first planarization layer is provided with a through hole, and the through hole penetrates the first planarization layer, to expose the first electrode pattern; and a second electrode layer, a second planarization layer and a third electrode layer that are disposed in stack on one side of the first planarization layer that is away from the substrate, wherein the second electrode layer is disposed closer to the substrate, the second electrode layer is connected to the first electrode pattern and the third electrode layer.

公开(公告)号：US12230683B2

公开(公告)日：2025-02-18

申请号：US17755380

申请日：2021-05-19

Applicant: BOE Technology Group Co., Ltd.

Inventor： Lizhong Wang ,  Ce Ning ,  Hehe Hu ,  Tianmin Zhou ,  Jipeng Song

IPC: H01L29/786 ,  H01L29/417

Abstract: The present disclosure provides a thin film transistor, a GOA circuit and an array substrate, the thin film transistor including a source electrode, including a source electrode wiring and a plurality of source electrode branches; a drain electrode, including a drain electrode wiring and a plurality of drain electrode branches; a gate; a semiconductor layer including a plurality of semiconductor branches; a plurality of source electrode branches. The plurality of drain electrode branches are in contact with the plurality of semiconductor branches and are divided into a plurality of cells; the source electrode wiring and the drain electrode wiring are arranged in a parallel and spaced apart, and the number m of one of the source electrode wiring and the drain electrode wiring is an integer greater than or equal to 2, and the number n of the other is an integer greater than or equal to 1.

公开(公告)号：US20240272497A1

公开(公告)日：2024-08-15

申请号：US18005421

申请日：2022-03-30

Applicant: BOE Technology Group Co., Ltd.

Inventor： Binbin Tong ,  Lizhong Wang ,  Jianbo Xian ,  Liping Lei ,  Chunping Long ,  Yunping Di ,  Ce Ning

IPC: G02F1/1362 ,  G02F1/1333 ,  G02F1/1343

CPC classification number: G02F1/136286 ,  G02F1/133308 ,  G02F1/13439

Abstract: At least one embodiment of the present disclosure provides a display panel, and the display panel includes: a first substrate and a second substrate oppositely combined with each other, the first substrate includes a base substrate, and a gate line, a first electrode, a first interlayer insulating layer, and second electrode on the base substrate; the first interlayer insulating layer includes a first via hole penetrating through the first interlayer insulating layer, the second electrode is electrically connected to the first electrode the first via hole, first support structure is provided in a region corresponding to the first via hole and on a side of the second electrode away from the base substrate; at least a part of the first support structure is located in the first via hole, an orthographic projection of the first via hole overlaps with an orthographic projection of the gate line on the base substrate.