公开(公告)号：US20240420646A1

公开(公告)日：2024-12-19

申请号：US18815723

申请日：2024-08-26

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Chen-Ming Chen ,  Hassan Edrees

IPC: G09G3/3266

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.

公开(公告)号：US20240210995A1

公开(公告)日：2024-06-27

申请号：US18483653

申请日：2023-10-10

Applicant: Apple Inc.

Inventor： Prashant Mandlik ,  Bhadrinarayana Lalgudi Visweswaran ,  Mahendra Chhabra ,  Chia-Hao Chang ,  Shiyi Liu ,  Siddharth Harikrishna Mohan ,  Zhen Zhang ,  Han-Chieh Chang ,  Yi Qiao ,  Yue Cui ,  Tyler R Kakuda ,  Michael Vosgueritchian ,  Sudirukkuge T. Jinasundera ,  Warren S Rieutort-Louis ,  Tsung-Ting Tsai ,  Jae Won Choi ,  Jiun-Jye Chang ,  Jean-Pierre S Guillou ,  Rui Liu ,  Po-Chun Yeh ,  Chieh Hung Yang ,  Ankit Mahajan ,  Takahide Ishii ,  Pei-Ling Lin ,  Pei Yin ,  Gwanwoo Park ,  Markus Einzinger ,  Martijn Kuik ,  Abhijeet S Bagal ,  Kyounghwan Kim ,  Jonathan H Beck ,  Chiang-Jen Hsiao ,  Chih-Hao Kung ,  Chih-Lei Chen ,  Chih-Yu Chung ,  Chuan-Jung Lin ,  Jung Yen Huang ,  Kuan-Chi Chen ,  Shinya Ono ,  Wei Jung Hsieh ,  Wei-Chieh Lin ,  Yi-Pu Chen ,  Yuan Ming Chiang ,  An-Di Sheu ,  Chi-Wei Chou ,  Chin-Fu Lee ,  Ko-Wei Chen ,  Kuan-Yi Lee ,  Weixin Li ,  Shin-Hung Yeh ,  Shyuan Yang ,  Themistoklis Afentakis ,  Asli Sirman ,  Baolin Tian ,  Han Liu

IPC: G06F1/16 ,  H10K59/131 ,  H10K59/40 ,  H10K77/10

CPC classification number: G06F1/1652 ,  H10K59/131 ,  H10K59/40 ,  H10K77/111 ,  H10K2102/311

Abstract: A display may have a stretchable portion with hermetically sealed rigid pixel islands. A flexible interconnect region may be interposed between the hermetically sealed rigid pixel islands. The hermetically sealed rigid pixel islands may include organic light-emitting diode (OLED) pixels. A conductive cutting structure may have an undercut that causes a discontinuity in a conductive OLED layer to mitigate lateral leakage. The conductive cutting structure may also be electrically connected to a cathode for the OLED pixels and provide a cathode voltage to the cathode. First and second inorganic passivation layers may be formed over the OLED pixels. Multiple discrete portions of an organic inkjet printed layer may be interposed between the first and second inorganic passivation layers.

公开(公告)号：US11966544B2

公开(公告)日：2024-04-23

申请号：US18323659

申请日：2023-05-25

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Suhwan Moon ,  Dong-Gwang Ha ,  Jiaxi Hu ,  Hao-Lin Chiu ,  Kwang Soon Park ,  Hassan Edrees ,  Wen-I Hsieh ,  Jiun-Jye Chang ,  Chin-Wei Lin ,  Kyung Wook Kim

IPC: G06F3/041 ,  G06F3/044 ,  G09G3/3208

CPC classification number: G06F3/04184 ,  G06F3/0412 ,  G06F3/0444 ,  G06F3/0446 ,  G09G3/3208 ,  G06F2203/04107 ,  G06F2203/04112

Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The display may include transistors with gate conductors, a first planarization layer formed over the gate conductors, one or more contacts formed in a first source-drain layer within the first planarization layer, a second planarization layer formed on the first planarization layer, one or more data lines formed in a second source-drain layer within the second planarization layer, a third planarization layer formed on the second planarization layer, and a data line shielding structure formed at least partly in a third source-drain layer within the third planarization layer. The data line shielding structure may be a routing line, a blanket layer, a mesh layer formed in one or more metal layers, and/or a data line covering another data line.

公开(公告)号：US20240096285A1

公开(公告)日：2024-03-21

申请号：US18358752

申请日：2023-07-25

Applicant: Apple Inc.

Inventor： Alper Ozgurluk ,  Andrew Lin ,  Cheuk Chi Lo ,  Chun-Ming Tang ,  Shinya Ono ,  Chun-Yao Huang

IPC: G09G3/3258 ,  G09G3/3266 ,  G09G3/3291

CPC classification number: G09G3/3258 ,  G09G3/3266 ,  G09G3/3291 ,  G09G2300/0842 ,  G09G2320/0233 ,  G09G2320/0247

Abstract: A display may include an array of pixels. A pixel can include an organic light-emitting diode, up to three thin-film transistors, and up to two capacitors. The pixel can include a drive transistor, an emission transistor, and a select transistor. The select transistor can be used to apply a reference voltage to the gate of the drive transistor during a global reset phase and during a global threshold voltage sampling phase and can also be used to apply a data voltage to the gate of the drive transistor during a data programming phase. The drive transistor can receive a power supply voltage that toggles between a low voltage during the global reset phase and a high voltage during other phases of operation. Configured and operated in this way, the pixel need not include separate dedicated anode reset and initialization transistors.

公开(公告)号：US11887546B2

公开(公告)日：2024-01-30

申请号：US18192905

申请日：2023-03-30

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee ,  Yun Wang ,  Fan Gui

IPC: G09G3/3258 ,  H01L29/786 ,  H10K59/121

CPC classification number: G09G3/3258 ,  H01L29/7869 ,  H10K59/1213 ,  G09G2300/0842 ,  G09G2320/0233 ,  G09G2320/043

Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.

公开(公告)号：US11861110B1

公开(公告)日：2024-01-02

申请号：US17956715

申请日：2022-09-29

Applicant: Apple Inc.

Inventor： Rungrot Kitsomboonloha ,  Donggeon Han ,  Jason N Gomez ,  Kyung Wook Kim ,  Nikolaus Hammler ,  Pei-En Chang ,  Saman Saeedi ,  Shih Chang Chang ,  Shinya Ono ,  Suk Won Hong ,  Szu-Hsien Lee ,  Victor H Yin ,  Young-Jik Jo ,  Yu-Heng Cheng ,  Joyan G Sanctis ,  Hongwoo Lee

IPC: G06F3/041 ,  G06F3/044 ,  H10K59/40

CPC classification number: G06F3/04182 ,  G06F3/044 ,  H10K59/40 ,  G06F3/0412 ,  G06F2203/04107 ,  G06F2203/04112

Abstract: An electronic device may have a display with touch sensors. One or more shielding layers may be interposed between the display and the touch sensors. The shielding layers may include shielding structures such as a conductive mesh structure and/or a transparent conductive film. The shielding structures may be actively driven or passively biased. In the active driving scheme, one or more inverting circuits may receive a noise signal from a cathode layer in the display and/or from the shielding structures, invert the received noise signal, and drive the inverted noise signal back onto the shielding structures to prevent any noise from the display from negatively impacting the performance of the touch sensors. In the passive biasing scheme, the shielding structures may be biased to a power supply voltage.

公开(公告)号：US11756481B2

公开(公告)日：2023-09-12

申请号：US17469816

申请日：2021-09-08

Applicant: Apple Inc.

Inventor： Hyunsoo Kim ,  Kingsuk Brahma ,  Myungjoon Choi ,  Yue Jack Chu ,  Li-Xuan Chuo ,  Hassan Edrees ,  Chin-Wei Lin ,  Hyunwoo Nho ,  Shinya Ono ,  Alex H. Pai ,  Jie Won Ryu ,  Yao Shi ,  Chaohao Wang

IPC: G09G3/3233 ,  G09G3/3266

CPC classification number: G09G3/3233 ,  G09G3/3266 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2320/0247 ,  G09G2320/041 ,  G09G2320/0626 ,  G09G2360/12

Abstract: Systems, methods, and devices are provided for mitigating visual artifacts by dynamically tuning bias voltages applied to display pixels. An electronic display may include a display pixel and a bias voltage supply. The bias voltage supply may supply a first bias voltage to the display pixel for a first subframe of a frame of image data. The bias voltage supply may supply a different second bias voltage to the display pixel for a second subframe of the frame of image data. This may mitigate certain image artifacts, such as flicker or variable refresh rate luminance difference, that could arise due to display pixel hysteresis that varies across subframes of the image frame.

公开(公告)号：US11741904B2

公开(公告)日：2023-08-29

申请号：US17206425

申请日：2021-03-19

Applicant: Apple Inc.

Inventor： Ting-Kuo Chang ,  Abbas Jamshidi Roudbari ,  Tsung-Ting Tsai ,  Warren S. Rieutort-Louis ,  Shinya Ono ,  Shin-Hung Yeh ,  Chien-Ya Lee ,  Shyuan Yang

IPC: G09G3/3275 ,  G09G3/3233 ,  G09G3/3266

CPC classification number: G09G3/3275 ,  G09G3/3233 ,  G09G3/3266 ,  G09G2310/021 ,  G09G2310/0297 ,  G09G2310/08

Abstract: A display may have rows and columns of pixels. Gate lines may be used to supply gate signals to rows of the pixels. Data lines may be used to supply data signals to columns of the pixels. The data lines may include alternating even and odd data lines. Data lines may be organized in pairs each of which includes one of the odd data lines and an adjacent one of the even data lines. Demultiplexer circuitry may be configured dynamically during data loading and pixel sensing operations. During data loading, data from display driver circuitry may be supplied, alternately to odd pairs of the data lines and even pairs of the data lines. During sensing, the demultiplexer circuitry may couple a pair of the even data lines to sensing circuitry in the display driver circuitry and then may couple a pair of the odd data lines to the sensing circuitry.

公开(公告)号：US11508309B2

公开(公告)日：2022-11-22

申请号：US17317128

申请日：2021-05-11

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee

IPC: G09G3/3266

Abstract: A display may include an array of pixels. Each pixel in the array may include a drive transistor, emission transistors, a data loading transistor, a gate voltage setting transistor, an initialization transistor, an anode reset transistor, a storage capacitor, and an optional current boosting capacitor. A data refresh may include a initialization phase, a threshold voltage sampling phase, and a data programming phase. The threshold voltage sampling phase can be substantially longer than the data programming phase to decrease a current sampling level during the threshold voltage sampling phase, which helps reduce the display luminance sensitivity to temperature variations.

公开(公告)号：US11348533B1

公开(公告)日：2022-05-31

申请号：US16864241

申请日：2020-05-01

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Gihoon Choo ,  Shiping Shen ,  Jie Won Ryu ,  Zino Lee ,  Hassan Edrees ,  Ting-Kuo Chang

IPC: G09G3/3266

Abstract: A display may include an array of pixels, where each pixel in the array includes an organic light-emitting diode coupled to associated thin-film transistors. The thin-film transistors may be controlled using at least first and second horizontal scan line signals. Loading different data values into any given row in the array may cause the scan line signals to exhibit varying rise/fall times, which results in horizontal crosstalk and luminance non-uniformity across the display. The rise and fall times of the second scan line signal are crucial, so the second scan line signal is driven by two separate scan line drivers formed on both sides of the display. Only the fall time of the first scan line signal is crucial, so the first scan line signal is driven by only one peripheral scan line driver and is coupled to an auxiliary pull-down circuit that is only activated during the pull-down transition.