公开(公告)号：US11757681B1

公开(公告)日：2023-09-12

申请号：US17934891

申请日：2022-09-23

Applicant: Apple Inc.

Inventor： Jose A. Tierno ,  Haiming Jin ,  Brian S. Leibowitz ,  Sanjeev K. Maheshwari ,  Chintan S. Thakkar

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03885

Abstract: To compensate for intersymbol interference, a serial data receiver circuit included in a computer system may include an equalizer circuit that includes a digital-to-analog converter circuit. Based on previously received symbols, the equalizer circuit modifies a signal received via a communication channel or link prior to clock and data recovery. In cases when the digital-to-analog converter circuit becomes saturated, the equalizer circuit additionally uses a dither signal to modify the received signal.