公开(公告)号：US12019566B2

公开(公告)日：2024-06-25

申请号：US16938364

申请日：2020-07-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sergey Blagodurov ,  Johnathan Alsop ,  Jagadish B. Kotra ,  Marko Scrbak ,  Ganesh Dasika

IPC: G06F13/16 ,  G06F9/30 ,  H04L45/122

CPC classification number: G06F13/1642 ,  G06F9/3004 ,  G06F9/30098 ,  G06F13/1663 ,  H04L45/122

Abstract: Arbitrating atomic memory operations, including: receiving, by a media controller, a plurality of atomic memory operations; determining, by an atomics controller associated with the media controller, based on one or more arbitration rules, an ordering for issuing the plurality of atomic memory operations; and issuing the plurality of atomic memory operations to a memory module according to the ordering.

公开(公告)号：US11868778B2

公开(公告)日：2024-01-09

申请号：US16937189

申请日：2020-07-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Ganesh Dasika ,  Sergey Blagodurov ,  Seyedmohammad Seyedzadehdelcheh

IPC: G06F9/34 ,  G06F9/30 ,  G06F13/16

CPC classification number: G06F9/342 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30167 ,  G06F13/1657

Abstract: Compacted addressing for transaction layer packets, including: determining, for a first epoch, one or more low entropy address bits in a plurality of first transaction layer packets; removing, from one or more memory addresses of one or more second transaction layer packets, the one or more low entropy address bits; and sending the one or more second transaction layer packets.

公开(公告)号：US20220365975A1

公开(公告)日：2022-11-17

申请号：US17564413

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Ganesh Dasika ,  Michael Ignatowski ,  Michael J. Schulte ,  Gabriel H. Loh ,  Valentina Salapura ,  Angela Beth Dalton

IPC: G06F16/901 ,  G06F15/80

Abstract: An accelerator device includes a first processing unit to access a structure of a graph dataset, and a second processing unit coupled with the first processing unit to perform computations based on data values in the graph dataset.

公开(公告)号：US20230205837A1

公开(公告)日：2023-06-29

申请号：US17561227

申请日：2021-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Laurent S. White ,  Ganesh Dasika ,  Saketh Venkata Rama

IPC: G06F17/13 ,  G06N20/00 ,  G01R33/24

CPC classification number: G06F17/13 ,  G06N20/00 ,  G01R33/24

Abstract: A physical system is simulated using a model including a plurality of elements in a mesh or grid. The elements are divided into partitions processed by different processing units. For some time steps, flux data is transmitted between partitions for updating the state of edge elements of the partitions. Periodically, transmission of flux data is suppressed and flux data is obtained by linear interpolation based on past flux data. Alternatively, flux data is obtained by processing state variables of an edge element and past flux data using a machine learning model, such as a DNN.

公开(公告)号：US20230169015A1

公开(公告)日：2023-06-01

申请号：US17539189

申请日：2021-11-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Kishore Punniyamurthy ,  SeyedMohammad SeyedzadehDelcheh ,  Sergey Blagodurov ,  Ganesh Dasika ,  Jagadish B. Kotra

IPC: G06F12/126

CPC classification number: G06F12/126 ,  G06F2212/6042

Abstract: A method includes storing a function representing a set of data elements stored in a backing memory and, in response to a first memory read request for a first data element of the set of data elements, calculating a function result representing the first data element based on the function.

公开(公告)号：US20230024089A1

公开(公告)日：2023-01-26

申请号：US17384646

申请日：2021-07-23

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Ganesh Dasika

IPC: G06F9/30

Abstract: A processing device includes a zero detection circuit to determine that an operand of a first instruction is zero and instruction conversion logic coupled with the zero detection circuit to, in response to the zero detection circuit determining that the operand is zero, convert the first instruction to a register move instruction executable by the processing device.

公开(公告)号：US20250004963A1

公开(公告)日：2025-01-02

申请号：US18217079

申请日：2023-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： William Peter Ehrett ,  Anthony Gutierrez ,  Vedula Venkata Srikant Bharadwaj ,  Karthik Ramu Sangaiah ,  Prachi Shukla ,  Sriseshan Srikanth ,  Ganesh Dasika ,  John Kalamatianos

IPC: G06F13/36

Abstract: A semiconductor device, referred to herein as a Globally Interconnected Operations (GIO) layer, provides global operations in the form of global data reduction for one or more PE arrays. The GIO layer includes processing elements that perform global data reduction on processing results from one or more PE arrays. The GIO layer includes connectors that allow it to be arranged in a 3D stack with one or more PE arrays, for example, on top of or beneath a PE array. This allows reduction operations to be implemented across PE arrays using an efficient topology with superior flexibility, scalability, latency and/or power characteristics that is customizable for particular use cases at assembly time, without requiring costly and time-consuming redesign of PE arrays, and without being constrained by particular PE array designs.

公开(公告)号：US11921784B2

公开(公告)日：2024-03-05

申请号：US17564413

申请日：2021-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Ganesh Dasika ,  Michael Ignatowski ,  Michael J Schulte ,  Gabriel H Loh ,  Valentina Salapura ,  Angela Beth Dalton

IPC: G06F15/80 ,  G06F16/901

CPC classification number: G06F16/9024 ,  G06F15/8046

Abstract: An accelerator device includes a first processing unit to access a structure of a graph dataset, and a second processing unit coupled with the first processing unit to perform computations based on data values in the graph dataset.

公开(公告)号：US11880312B2

公开(公告)日：2024-01-23

申请号：US17539189

申请日：2021-11-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Kishore Punniyamurthy ,  SeyedMohammad SeyedzadehDelcheh ,  Sergey Blagodurov ,  Ganesh Dasika ,  Jagadish B Kotra

IPC: G06F12/00 ,  G06F12/126 ,  G06F12/0855

CPC classification number: G06F12/126 ,  G06F12/0859 ,  G06F2212/1024 ,  G06F2212/6042

Abstract: A method includes storing a function representing a set of data elements stored in a backing memory and, in response to a first memory read request for a first data element of the set of data elements, calculating a function result representing the first data element based on the function.

公开(公告)号：US20220365725A1

公开(公告)日：2022-11-17

申请号：US17741403

申请日：2022-05-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael Ignatowski ,  Valentina Salapura ,  Ganesh Dasika ,  Gabriel H Loh

IPC: G06F3/06

Abstract: A method includes receiving from a compute element a command for performing a requested operation on data stored in a memory device, and in response to receiving the command, performing the requested operation by generating a plurality of memory access requests based on the command and issuing the plurality of memory access requests to the memory device.