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公开(公告)号：US20230393855A1
公开(公告)日：2023-12-07
申请号：US17833504
申请日：2022-06-06
Applicant: Advanced Micro Devices, Inc.
Inventor： Gabriel H. Loh , Yasuko Eckert , Bradford Beckmann , Michael Estlick , Jay Fleischman
CPC classification number: G06F9/3887 , G06F9/3877 , G06F9/30098 , G06F9/3555
Abstract: An approach is provided for implementing register based single instruction, multiple data (SIMD) lookup table operations. According to the approach, an instruction set architecture (ISA) can support one or more SIMD instructions that enable vectors or multiple values in source data registers to be processed in parallel using a lookup table or truth table stored in one or more function registers. The SIMD instructions can be flexibly configured to support functions with inputs and outputs of various sizes and data formats. Various approaches are also described for supporting very large lookup tables that span multiple registers.
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公开(公告)号：US12118411B2
公开(公告)日：2024-10-15
申请号：US16568038
申请日：2019-09-11
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Sneha V. Desai , Michael Estlick , Erik Swanson , Anilkumar Ranganagoudra
CPC classification number: G06F9/544 , G06F9/505 , G06F9/5083 , G06F9/528 , G06F9/546
Abstract: A processor includes a plurality of execution pipes and a distributed scheduler coupled to the plurality of execution pipes. The distributed scheduler includes a first queue to buffer instruction operations from a front end of an instruction pipeline of the processor and a plurality of second queues, wherein each second queue is to buffer instruction operations allocated from the first queue for a corresponding separate subset of execution pipes of the plurality of execution pipes. The distributed scheduler further includes a queue controller to select an allocation mode from a plurality of allocation modes based on whether at least one indicator of an imbalance at the distributed scheduler is detected, and further to control the distributed scheduler to allocate instruction operations from the first queue among the plurality of second queues in accordance with the selected allocation mode.
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公开(公告)号：US11960897B2
公开(公告)日：2024-04-16
申请号：US17389838
申请日：2021-07-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Michael Estlick , Erik Swanson , Eric Dixon , Todd Baumgartner
CPC classification number: G06F9/3869 , G06F9/30123
Abstract: In some implementations, a processor includes a plurality of parallel instruction pipes, a register file includes at least one shared read port configured to be shared across multiple pipes of the plurality of parallel instruction pipes. Control logic controls multiple parallel instruction pipes to read from the at least one shared read port. In certain examples, the at least one shared register file read port is coupled as a single read port for one of the parallel instruction pipes and as a shared register file read port for a plurality of other parallel instruction pipes.
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公开(公告)号：US20240095180A1
公开(公告)日：2024-03-21
申请号：US18088170
申请日：2022-12-23
Applicant: Advanced Micro Devices, Inc.
Inventor： Gabriel H. Loh , Michael Estlick , Jay Fleischman , Michael J. Schulte , Bradford Beckmann , Yasuko Eckert
IPC: G06F12/1009
CPC classification number: G06F12/1009 , G06F2212/1008
Abstract: The disclosed computer-implemented method for interpolating register-based lookup tables can include identifying, within a set of registers, a lookup table that has been encoded for storage within the set of registers. The method can also include receiving a request to look up a value in the lookup table and responding to the request by interpolating, from the encoded lookup table stored in the set of registers, a representation of the requested value. Various other methods, systems, and computer-readable media are also disclosed.
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公开(公告)号：US11842200B2
公开(公告)日：2023-12-12
申请号：US16586247
申请日：2019-09-27
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： John M. King , Magiting Talisayon , Michael Estlick
CPC classification number: G06F9/3887 , G06F9/3013 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F9/3861
Abstract: An apparatus includes a plurality of load buses and a load store unit that includes a plurality of load ports to access the plurality of load buses. The load store unit performs a gather operation to concurrently gather a plurality of subsets of data from a memory via the plurality of load buses in a first mode. The apparatus also includes a register that is partitioned into a plurality of portions to hold the plurality of subsets of data provided by the load store unit. The load store unit ignores exceptions or faults while performing the gather operation in the first mode and transitions to a second mode in response to an exception or fault. Two lanes are dispatched to concurrently perform the gather operation per clock cycle in the first mode and a single lane is dispatched to perform the gather operation per clock cycle in the second mode.
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Patent Agency Ranking
公开(公告)号：US20140372732A1
公开(公告)日：2014-12-18
申请号：US13918863
申请日：2013-06-14
Applicant: Advanced Micro Devices, Inc.
Inventor： Jay Fleischman , Michael Estlick
IPC: G06F9/38
CPC classification number: G06F9/384 , G06F9/3842 , G06F9/3859 , G06F9/3861
Abstract: A method includes undoing, in reverse program order, changes in a state of a processing device caused by speculative instructions previously dispatched for execution in the processing device and concurrently deallocating resources previously allocated to the speculative instructions in response to interruption of dispatch of instructions due to a flush of the speculative instructions. A processor device comprises a retire queue to store entries for instructions that are awaiting retirement and a finite state machine. The finite state machine is to interrupt dispatch of instructions in response to a flush of speculative instructions previously dispatched for execution in the processing device and to undo, in reverse program order, changes in a state of the processing device caused by the speculative instructions while concurrently deallocating resources previously allocated to the speculative instructions.
Abstract translation: 一种方法包括以反向程序顺序来撤销由先前在处理设备中执行的推测性指令引起的处理设备的状态的改变，并且响应于由于指令的发送中断而先前分配给推测指令的资源 冲突的投机指示。 处理器设备包括用于存储等待退休的指令的条目的退出队列和有限状态机。 有限状态机是响应于先前调度以在处理设备中执行的推测性指令的刷新来中断指令的分派，并且以反向程序顺序撤销由推测指令引起的处理设备的状态的改变，同时 释放以前分配给投机指示的资源。
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公开(公告)号：US20240319964A1
公开(公告)日：2024-09-26
申请号：US18126107
申请日：2023-03-24
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Onur Kayiran , Lee Evan Eisen , Michael Estlick , Jay Fleischman , Matthew R. Poremba , Gabriel H. Loh
IPC: G06F7/503
CPC classification number: G06F7/503
Abstract: A processor includes one or more processor cores configured to perform accumulate top (ACCT) and accumulate bottom (ACCB) instructions. To perform such instructions, at least one processor core of the processor includes an ACCT data path that adds a first portion of a block of data to a first lane of a set of lanes of a top accumulator and adds a carry-out bit to a second lane of the set of lanes of the top accumulator. Further, the at least one processor core includes an ACCB data path that adds a second portion of the block of data to a first lane of a set of lanes of a bottom accumulator and adds a carry-out bit to a second lane of the set of lanes of the bottom accumulator.
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公开(公告)号：US20240111489A1
公开(公告)日：2024-04-04
申请号：US17955634
申请日：2022-09-29
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Onur Kayiran , Michael Estlick , Masab Ahmad , Gabriel H. Loh
CPC classification number: G06F7/4981 , G06F7/506
Abstract: A processing unit includes a plurality of adders and a plurality of carry bit generation circuits. The plurality of adders add first and second X bit binary portion values of a first Y bit binary value and a second Y bit binary value. Y is a multiple of X. The plurality of adders further generate first carry bits. The plurality of carry bit generation circuits is coupled to the plurality of adders, respectively, and receive the first carry bits. The plurality of carry bit generation circuits generate second carry bits based on the first carry bits. The plurality of adders use the second carry bits to add the first and second X bit binary portions of the first and second Y bit binary values, respectively.
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公开(公告)号：US20230032375A1
公开(公告)日：2023-02-02
申请号：US17390293
申请日：2021-07-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Eric Busta , Michael L. Golden , Sean M. O'Mullan , James Wingfield , Keith A. Kasprak , Russell Schreiber , Michael Estlick
Abstract: An integrated circuit includes one or more processing units that execute instructions that employ a register file, control logic creates a pre-startup register free list, prior to normal operation of at least one of the processing units, that includes a list of registers devoid of undefective registers. In some implementations, no column and row repair information is provided to register file repair logic. In certain examples, the register file is configured as a repair-less register file. During normal operation of the one or more processing units, the integrated circuit employs the pre-startup register free list to select registers in a register file for the executing instructions. Associated methods are also presented.
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10.发明授权公开(公告)号：US11567554B2
公开(公告)日：2023-01-31
申请号：US15837918
申请日：2017-12-11
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Jay Fleischman , Michael Estlick , Michael Christopher Sedmak , Erik Swanson , Sneha V. Desai
Abstract: A pipeline includes a first portion configured to process a first subset of bits of an instruction and a second portion configured to process a second subset of the bits of the instruction. A first clock mesh is configured to provide a first clock signal to the first portion of the pipeline. A second clock mesh is configured to provide a second clock signal to the second portion of the pipeline. The first and second clock meshes selectively provide the first and second clock signals based on characteristics of in-flight instructions that have been dispatched to the pipeline but not yet retired. In some cases, a physical register file is configured to store values of bits representative of instructions. Only the first subset is stored in the physical register file in response to the value of the zero high bit indicating that the second subset is equal to zero.
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