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    BIGNUM ADDITION AND/OR SUBTRACTION WITH CARRY PROPAGATION
    1.
    发明公开
    BIGNUM ADDITION AND/OR SUBTRACTION WITH CARRY PROPAGATION 审中-公开

    公开(公告)号：US20240111489A1

    公开(公告)日：2024-04-04

    申请号：US17955634

    申请日：2022-09-29

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： Onur Kayiran ,  Michael Estlick ,  Masab Ahmad ,  Gabriel H. Loh

    IPC分类号： G06F7/498 ,  G06F7/506

    CPC分类号： G06F7/4981 ,  G06F7/506

    摘要： A processing unit includes a plurality of adders and a plurality of carry bit generation circuits. The plurality of adders add first and second X bit binary portion values of a first Y bit binary value and a second Y bit binary value. Y is a multiple of X. The plurality of adders further generate first carry bits. The plurality of carry bit generation circuits is coupled to the plurality of adders, respectively, and receive the first carry bits. The plurality of carry bit generation circuits generate second carry bits based on the first carry bits. The plurality of adders use the second carry bits to add the first and second X bit binary portions of the first and second Y bit binary values, respectively.

    SCATTER REDUCTION INSTRUCTION
    2.
    发明申请
    SCATTER REDUCTION INSTRUCTION 审中-公开

    公开(公告)号：US20170185414A1

    公开(公告)日：2017-06-29

    申请号：US15301206

    申请日：2015-12-24

    申请人： INTEL CORPORATION

    发明人： Jun Jin ,  Elmoustapha Ould-Ahmed-Vall

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3887 ,  G06F7/485 ,  G06F7/4981 ,  G06F9/30 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/3016 ,  G06F15/8007

    摘要： Single Instruction, Multiple Data (SIMD) technologies are described. A processing device can include a processor core and a memory. The processor core can receive, from a software application, a request to perform an operation on a first set of variables that includes a first input value and a register value and perform the operation on a second set of variables that includes a second input value and the first register value. The processor core can vectorize the operation on the first set of variables and the second set of variables. The processor core can perform the operation on the first set of variables and the second set of variables in parallel to obtain a first operation value and a second operation value. The processor core can perform a horizontal add operation on the first operation value and the second operation value and write the result to memory.

    Decimal point processing apparatus
    3.
    发明授权
    Decimal point processing apparatus 失效
    十进制点处理装置

    公开(公告)号：US3571808A

    公开(公告)日：1971-03-23

    申请号：US3571808D

    申请日：1968-12-06

    申请人： SHARP KK

    发明人： WASHIZUKA ISAMU ,  TERAMURA SATOSHI ,  HANAHARA HITOSHI

    IPC分类号： G06F7/48 ,  G06F7/491 ,  G06F7/50 ,  G06F15/02 ,  G11C19/18 ,  G11B13/00

    CPC分类号： G06F7/491 ,  G06F7/4981 ,  G06F15/02 ,  G11C19/184

    摘要： A computer having registers in which a plurality of memory cells are connected in cascade in correspondence with the desired number of bits, only one of said memory cells is arranged to have an operational state different from those of all of the other memory cells and the bit location of said memory cell having the operational state (memory state) different from the others is caused to correspond to a numerical value to be stored, means of shifting said bit location of said memory cell having the operational state different from the others to another bit location, and shift control means for determining said bit location to which said bit location of said memory cell having the operational state different from the others is to be shifted in correspondence with a numerical value to be arithmetically operated as one operand with respect to said numerical value already stored in the register.