公开(公告)号：US11567554B2

公开(公告)日：2023-01-31

申请号：US15837918

申请日：2017-12-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jay Fleischman ,  Michael Estlick ,  Michael Christopher Sedmak ,  Erik Swanson ,  Sneha V. Desai

IPC: G06F1/32 ,  G06F1/324 ,  G06F9/38 ,  G06F13/38 ,  G06F9/30

Abstract: A pipeline includes a first portion configured to process a first subset of bits of an instruction and a second portion configured to process a second subset of the bits of the instruction. A first clock mesh is configured to provide a first clock signal to the first portion of the pipeline. A second clock mesh is configured to provide a second clock signal to the second portion of the pipeline. The first and second clock meshes selectively provide the first and second clock signals based on characteristics of in-flight instructions that have been dispatched to the pipeline but not yet retired. In some cases, a physical register file is configured to store values of bits representative of instructions. Only the first subset is stored in the physical register file in response to the value of the zero high bit indicating that the second subset is equal to zero.

公开(公告)号：US11507158B2

公开(公告)日：2022-11-22

申请号：US16872602

申请日：2020-05-12

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Xiuting Kaleen Cheng Man ,  Erik Swanson ,  Larry D. Hewitt ,  Adam N. C. Clark

IPC: G06F1/26

Abstract: Electrical design current throttling, including: applying an electrical design current (EDC) threshold for each control processing unit component of a plurality of the central processing unit components responsive to the corresponding priority of each central processing unit component, the priority of a central processing unit component responsive to a central processing unit component's current usage data.

公开(公告)号：US12118411B2

公开(公告)日：2024-10-15

申请号：US16568038

申请日：2019-09-11

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Sneha V. Desai ,  Michael Estlick ,  Erik Swanson ,  Anilkumar Ranganagoudra

IPC: G06F9/54 ,  G06F9/50 ,  G06F9/52

CPC classification number: G06F9/544 ,  G06F9/505 ,  G06F9/5083 ,  G06F9/528 ,  G06F9/546

Abstract: A processor includes a plurality of execution pipes and a distributed scheduler coupled to the plurality of execution pipes. The distributed scheduler includes a first queue to buffer instruction operations from a front end of an instruction pipeline of the processor and a plurality of second queues, wherein each second queue is to buffer instruction operations allocated from the first queue for a corresponding separate subset of execution pipes of the plurality of execution pipes. The distributed scheduler further includes a queue controller to select an allocation mode from a plurality of allocation modes based on whether at least one indicator of an imbalance at the distributed scheduler is detected, and further to control the distributed scheduler to allocate instruction operations from the first queue among the plurality of second queues in accordance with the selected allocation mode.

公开(公告)号：US11960897B2

公开(公告)日：2024-04-16

申请号：US17389838

申请日：2021-07-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael Estlick ,  Erik Swanson ,  Eric Dixon ,  Todd Baumgartner

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3869 ,  G06F9/30123

Abstract: In some implementations, a processor includes a plurality of parallel instruction pipes, a register file includes at least one shared read port configured to be shared across multiple pipes of the plurality of parallel instruction pipes. Control logic controls multiple parallel instruction pipes to read from the at least one shared read port. In certain examples, the at least one shared register file read port is coupled as a single read port for one of the parallel instruction pipes and as a shared register file read port for a plurality of other parallel instruction pipes.

公开(公告)号：US20240004664A1

公开(公告)日：2024-01-04

申请号：US17855727

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Sree Harsha Kosuru ,  Eric Dixon ,  Erik Swanson ,  Michael Estlick ,  Patrick Michael Lowry

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/384 ,  G06F9/30123

Abstract: The disclosed system may include a processor configured to detect that a data unit size for an instruction is smaller than a register. The processor may allocate a first portion of the register to the instruction in a manner that leaves a second portion of the register available for allocating to an additional instruction. The processor may also track the register as a split register. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11573801B1

公开(公告)日：2023-02-07

申请号：US17489301

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Eric Dixon ,  Erik Swanson ,  Theodore Carlson ,  Ruchir Dalal ,  Michael Estlick

IPC: G06F9/38 ,  G06F9/48 ,  G06F9/30

Abstract: A processor includes a register file and control logic that detects multiple different sets of sequential zero bits of a register in the register file, wherein each of the multiple different sets has a bit length that corresponds to a partial instruction width and operates at a first partial instruction width or a second partial instruction width with the register file depending on number of sets of zero bits detected in the register. In certain examples, the control logic causes operating at first instruction width that avoids merging of a first bit length of data in the register and operating at the second instruction width that avoids merging of a second bit length of data in the register. In some examples, a register rename map table incudes multiple zero bits that identify the detected multiple different sets of bits of sequential zeros.

公开(公告)号：US11544065B2

公开(公告)日：2023-01-03

申请号：US16585817

申请日：2019-09-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Arun A. Nair ,  Todd Baumgartner ,  Michael Estlick ,  Erik Swanson

IPC: G06F9/30

Abstract: A processor includes a front-end with an instruction set that operates at a first bit width and a floating point unit coupled to receive the instruction set in the processor that operates at the first bit width. The floating point unit operates at a second bit width and, based upon a bit width assessment of the instruction set provided to the floating point unit, the floating point unit employs a shadow-latch configured floating point register file to perform bit width reconfiguration. The shadow-latch configured floating point register file includes a plurality of regular latches and a plurality of shadow latches for storing data that is to be either read from or written to the shadow latches. The bit width reconfiguration enables the floating point unit that operates at the second bit width to operate on the instruction set received at the first bit width.

公开(公告)号：US12229563B2

公开(公告)日：2025-02-18

申请号：US17855727

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Sree Harsha Kosuru ,  Eric Dixon ,  Erik Swanson ,  Michael Estlick ,  Patrick Michael Lowry

IPC: G06F9/30 ,  G06F9/38

Abstract: The disclosed system may include a processor configured to detect that a data unit size for an instruction is smaller than a register. The processor may allocate a first portion of the register to the instruction in a manner that leaves a second portion of the register available for allocating to an additional instruction. The processor may also track the register as a split register. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US12204935B2

公开(公告)日：2025-01-21

申请号：US17390149

申请日：2021-07-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael Estlick ,  Erik Swanson ,  Eric Dixon

IPC: G06F9/48 ,  G06F9/38

Abstract: Methods, systems, and apparatuses provide support for allowing thread forward progress in a processing system and that improves quality of service. One system includes a processor; a bus coupled to the processor; a memory coupled to the processor via the bus; and a floating point unit coupled to the processor via the bus, wherein floating point unit comprises hardware control logic operative to: store for each thread, by a scheduler of the floating point unit, a counter; increase, by the scheduler, a value of the counter for each thread corresponding to a thread when at least one source ready operation exist for the thread; compare, by the scheduler, the value of the counter to a predetermined threshold; and make other threads ineligible to be picked by the scheduler when the counter is greater than or equal to the predetermined threshold.

公开(公告)号：US11847463B2

公开(公告)日：2023-12-19

申请号：US16585973

申请日：2019-09-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Kai Troester ,  Scott Thomas Bingham ,  John M. King ,  Michael Estlick ,  Erik Swanson ,  Robert Weidner

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/30036 ,  G06F9/30038 ,  G06F9/30043 ,  G06F9/3887 ,  G06F9/30018

Abstract: A processor includes a load/store unit and an execution pipeline to execute an instruction that represents a single-instruction-multiple-data (SIMD) operation, and which references a memory block storing operand data for one or more lanes of a plurality of lanes and a mask vector indicating which lanes of a plurality of lanes are enabled and which are disabled for the operation. The execution pipeline executes an instruction in a first execution mode unless a memory fault is generated during execution of the instruction in the first execution mode. In response to the memory fault, the execution pipeline re-executes the instruction in a second execution mode. In the first execution mode, a single load operation is attempted to access the memory block via the load/store unit. In the second execution mode, a separate load operation is performed by the load/store unit for each enabled lane of the plurality of lanes prior to executing the SIMD operation.