公开(公告)号：US11544065B2

公开(公告)日：2023-01-03

申请号：US16585817

申请日：2019-09-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Arun A. Nair ,  Todd Baumgartner ,  Michael Estlick ,  Erik Swanson

IPC: G06F9/30

Abstract: A processor includes a front-end with an instruction set that operates at a first bit width and a floating point unit coupled to receive the instruction set in the processor that operates at the first bit width. The floating point unit operates at a second bit width and, based upon a bit width assessment of the instruction set provided to the floating point unit, the floating point unit employs a shadow-latch configured floating point register file to perform bit width reconfiguration. The shadow-latch configured floating point register file includes a plurality of regular latches and a plurality of shadow latches for storing data that is to be either read from or written to the shadow latches. The bit width reconfiguration enables the floating point unit that operates at the second bit width to operate on the instruction set received at the first bit width.

公开(公告)号：US12190117B2

公开(公告)日：2025-01-07

申请号：US16697147

申请日：2019-11-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Neil N. Marketkar ,  Arun A. Nair

IPC: G06F9/38 ,  G06F9/30

Abstract: Techniques are provided for allocating registers for a processor. The techniques include identifying a first instruction of an instruction dispatch set that meets all register allocation suppression criteria of a first set of register allocation suppression criteria, suppressing register allocation for the first instruction, identifying a second instruction of the instruction dispatch set that does not meet all register allocation suppression criteria of a second set of register allocation suppression criteria, and allocating a register for the second instruction.

公开(公告)号：US11281466B2

公开(公告)日：2022-03-22

申请号：US16660495

申请日：2019-10-22

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Arun A. Nair ,  Michael Estlick ,  Erik Swanson ,  Sneha V. Desai ,  Donglin Ji

IPC: G06F9/30 ,  G06F9/38

Abstract: A floating point unit includes a non-pickable scheduler queue (NSQ) that offers a load operation concurrently with a load store unit retrieving load data for an operand that is to be loaded by the load operation. The floating point unit also includes a renamer that renames architectural registers used by the load operation and allocates physical register numbers to the load operation in response to receiving the load operation from the NSQ. The floating point unit further includes a set of pickable scheduler queues that receive the load operation from the renamer and store the load operation prior to execution. A physical register file is implemented in the floating point unit and a free list is used to store physical register numbers of entries in the physical register file that are available for allocation.

公开(公告)号：US11599359B2

公开(公告)日：2023-03-07

申请号：US16877112

申请日：2020-05-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Arun A. Nair ,  Ashok T. Venkatachar ,  Emil Talpes ,  Srikanth Arekapudi ,  Rajesh Kumar Arunachalam

IPC: G06F9/30 ,  G06F9/38

Abstract: A processor in a data processing system includes a master-shadow physical register file and a renaming unit. The master-shadow physical register file has a master storage coupled to shadow storage. The renaming unit is coupled to the master-shadow physical register file. Based on an occurrence of shadow transfer activation conditions verified by the renaming unit, data in the master storage is transferred from the master storage to the shadow storage for storage. Data is transferred from the shadow storage back to the master storage based on the occurrence of a shadow-to-master transfer event, which includes, for example, a flush of the master storage by the processor.

公开(公告)号：US20210157598A1

公开(公告)日：2021-05-27

申请号：US16697147

申请日：2019-11-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Neil N. Marketkar ,  Arun A. Nair

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/50

Abstract: Techniques are provided for allocating registers for a processor. The techniques include identifying a first instruction of an instruction dispatch set that meets all register allocation suppression criteria of a first set of register allocation suppression criteria, suppressing register allocation for the first instruction, identifying a second instruction of the instruction dispatch set that does not meet all register allocation suppression criteria of a second set of register allocation suppression criteria, and allocating a register for the second instruction.