公开(公告)号：US20240004657A1

公开(公告)日：2024-01-04

申请号：US17855621

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Rajesh Kumar Arunachalam ,  Manivannan Bhoopathy ,  Hon-Hin Wong ,  Scott Thomas Bingham

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/3838

Abstract: The disclosed system may include a processor configured to encode, using an encoding scheme that reduces a number of bits needed to represent one or more instructions from a set of instructions in an instruction buffer represented by a dependency matrix, a dependency indicating that a child instruction represented in the dependency matrix depends on a parent instruction represented in the dependency matrix. The processor may also be configured to store the encoded dependency in the dependency matrix and dispatch instructions in the instruction buffer based at least on decoding one or more dependencies stored in the dependency matrix for the instructions. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US12118357B2

公开(公告)日：2024-10-15

申请号：US17855621

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Rajesh Kumar Arunachalam ,  Manivannan Bhoopathy ,  Hon-Hin Wong ,  Scott Thomas Bingham

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/3838

Abstract: The disclosed system may include a processor configured to encode, using an encoding scheme that reduces a number of bits needed to represent one or more instructions from a set of instructions in an instruction buffer represented by a dependency matrix, a dependency indicating that a child instruction represented in the dependency matrix depends on a parent instruction represented in the dependency matrix. The processor may also be configured to store the encoded dependency in the dependency matrix and dispatch instructions in the instruction buffer based at least on decoding one or more dependencies stored in the dependency matrix for the instructions. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11599359B2

公开(公告)日：2023-03-07

申请号：US16877112

申请日：2020-05-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Arun A. Nair ,  Ashok T. Venkatachar ,  Emil Talpes ,  Srikanth Arekapudi ,  Rajesh Kumar Arunachalam

IPC: G06F9/30 ,  G06F9/38

Abstract: A processor in a data processing system includes a master-shadow physical register file and a renaming unit. The master-shadow physical register file has a master storage coupled to shadow storage. The renaming unit is coupled to the master-shadow physical register file. Based on an occurrence of shadow transfer activation conditions verified by the renaming unit, data in the master storage is transferred from the master storage to the shadow storage for storage. Data is transferred from the shadow storage back to the master storage based on the occurrence of a shadow-to-master transfer event, which includes, for example, a flush of the master storage by the processor.