公开(公告)号：US08629019B2

公开(公告)日：2014-01-14

申请号：US10254385

申请日：2002-09-24

申请人： Robert Q. Xu ,  Jacek Korec

发明人： Robert Q. Xu ,  Jacek Korec

IPC分类号： H01L21/336

CPC分类号： H01L21/76897 ,  H01L29/407 ,  H01L29/7813

摘要： A method for providing self aligned contacts for a trench power MOSFET is disclosed. The method includes, etching trenches in a substrate through a mask of silicon nitride deposited on an oxide layer, forming a gate oxide layer on the walls of the trenches, applying polysilicon to fill the trenches and to cover the surface of the mask of silicon nitride, removing the polysilicon from the surface of the mask of silicon nitride and applying a photoresist mask to cover a location of a gate bus. The method further includes recessing polysilicon plugs formed in trenches that are located in the active area to form recesses above the polysilicon plugs, filling recesses formed above the polysilicon plugs formed in trenches that are located in the active area with an insulator, applying a fourth photo resist mask to define contact windows that are opened in the nitride layer, and selectively etching the silicon nitride film and leaving flat surfaced oxide buttons covering the trenches that are located in the active area. Moreover, electric contact trenches are defined using self-aligned spacer operations, and a fifth photo resist mask is applied to pattern metal contacts that reach the semiconductor device active areas.

摘要翻译： 公开了一种用于为沟槽功率MOSFET提供自对准触点的方法。 该方法包括：通过沉积在氧化物层上的氮化硅掩模蚀刻衬底中的沟槽，在沟槽的壁上形成栅极氧化层，施加多晶硅以填充沟槽并覆盖氮化硅掩模的表面 从氮化硅掩模的表面去除多晶硅并施加光致抗蚀剂掩模以覆盖栅极总线的位置。 该方法还包括凹陷形成在沟槽中的多晶硅插塞，其位于有源区域中，以在多晶硅插塞之上形成凹陷，在形成于有源区域的沟槽中形成的多晶硅插塞之上形成一个绝缘体，从而施加第四张照片 抗蚀剂掩模以限定在氮化物层中打开的接触窗口，并且选择性地蚀刻氮化硅膜并留下覆盖位于有源区域中的沟槽的平坦的表面氧化物按钮。 此外，使用自对准间隔物操作限定电接触沟槽，并且将第五光致抗蚀剂掩模施加到到达半导体器件有源区域的图案金属接触。

公开(公告)号：US07420247B2

公开(公告)日：2008-09-02

申请号：US11202981

申请日：2005-08-12

申请人： Shuming Xu ,  Jacek Korec

发明人： Shuming Xu ,  Jacek Korec

IPC分类号： H01L29/72

CPC分类号： H01L29/7835 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4933

摘要： A LDMOS transistor comprises a trench formed through the epitaxial layer at least to the top surface of the substrate, the trench having a bottom surface and a sidewall contacting the source region and the portion of the channel region extending under the source region. A first insulating layer is formed over the upper surface and sidewall surfaces of the conductive gate. A continuous layer of conductive material forming a source contact and a gate shield electrode is formed along the bottom surface and the sidewall of the trench and over the first insulating layer to cover the top and sidewall surfaces of the conductive gate. A second insulating layer is formed over an active area of the transistor, including over the continuous layer of conductive material and filling the trench. A drain electrode can extend over the second insulating layer to substantially cover the active area.

摘要翻译： LDMOS晶体管包括至少通过外延层形成的沟槽，至少到衬底的顶表面，沟槽具有接触源极区域和在源极区域下延伸的沟道区域的部分的底表面和侧壁。 在导电栅极的上表面和侧壁表面上形成第一绝缘层。 形成源极接触和栅极屏蔽电极的连续导电材料层沿着沟槽的底表面和侧壁形成，并且在第一绝缘层上方覆盖导电栅极的顶表面和侧壁表面。 在晶体管的有源区域上形成第二绝缘层，包括在连续的导电材料层上并填充沟槽。 漏电极可以在第二绝缘层上延伸以基本覆盖有源区。

公开(公告)号：US07235845B2

公开(公告)日：2007-06-26

申请号：US11202968

申请日：2005-08-12

申请人： Shuming Xu ,  Jacek Korec

发明人： Shuming Xu ,  Jacek Korec

IPC分类号： H01L29/76

CPC分类号： H01L29/7835 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/456 ,  H01L29/4933

摘要： A laterally diffused metal-oxide-semiconductor (LDMOS) transistor device includes a doped substrate having an epitaxial layer thereover having source and drain implant regions and body and lightly doped drain regions formed therein. The channel region and lightly doped drain regions are doped to a depth to abut the top surface of the substrate. In alternative embodiments, a buffer region of the second conductivity type and having dopant concentration greater than or equal to about the channel region is formed over the top surface of the substrate between the top surface of the substrate and the channel region and lightly doped drain region, wherein the channel region and lightly doped drain regions are doped to a depth to abut the buffer region.

摘要翻译： 横向扩散的金属氧化物半导体（LDMOS）晶体管器件包括具有外延层的掺杂衬底，其具有源极和漏极注入区域以及在其中形成的体和轻掺杂漏极区域。 沟道区域和轻掺杂漏极区域被掺杂到与衬底的顶表面邻接的深度。 在替代实施例中，在衬底的顶表面和沟道区和轻掺杂漏极区之间的衬底的顶表面上形成第二导电类型的缓冲区，并且具有大于或等于沟道区的掺杂浓度 ，其中沟道区域和轻掺杂漏极区域被掺杂到深度以邻接缓冲区域。

公开(公告)号：US20070138548A1

公开(公告)日：2007-06-21

申请号：US11676613

申请日：2007-02-20

申请人： Christopher Kocon ,  Shuming Xu ,  Jacek Korec

发明人： Christopher Kocon ,  Shuming Xu ,  Jacek Korec

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4933 ,  H01L29/7802 ,  H01L29/7816 ,  H01L29/7823

摘要： A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is formed in the semiconductor layer. A conductive gate is formed over a gate dielectric layer that is formed over a channel region. A drain contact electrically connects the drain extension region to the substrate and is laterally spaced from the channel region. The drain contact includes a highly-doped drain contact region formed between the substrate and the drain extension region in the semiconductor layer, wherein a topmost portion of the highly-doped drain contact region is spaced from the upper surface of the semiconductor layer. A source contact electrically connects the source region to the body region.

摘要翻译： 横向扩散的金属氧化物半导体晶体管器件包括具有在衬底上形成的半导体层的第一导电类型的衬底。 在半导体层中形成第一导电类型的源极区域和漏极延伸区域。 在半导体层中形成第二导电类型的体区。 导电栅极形成在沟道区域上形成的栅极电介质层上。 漏极接触将漏极延伸区域电连接到衬底并且与沟道区域横向间隔开。 漏极接触包括形成在半导体层中的衬底和漏极延伸区域之间的高掺杂漏极接触区域，其中高掺杂漏极接触区域的最高部分与半导体层的上表面间隔开。 源极触点将源极区域电连接到主体区域。

公开(公告)号：US09136060B2

公开(公告)日：2015-09-15

申请号：US11966965

申请日：2007-12-28

申请人： Haim Goldberger ,  Sik Lui ,  Jacek Korec ,  Y. Mohammed Kasem ,  Harianto Wong ,  Jack Van Den Heuvel

发明人： Haim Goldberger ,  Sik Lui ,  Jacek Korec ,  Y. Mohammed Kasem ,  Harianto Wong ,  Jack Van Den Heuvel

IPC分类号： H01L21/20 ,  H01G4/33 ,  H01G4/38 ,  H01L49/02 ,  H01L29/94 ,  H01L29/66 ,  H01L23/48

CPC分类号： H01G4/33 ,  H01G4/38 ,  H01L23/481 ,  H01L28/40 ,  H01L29/66181 ,  H01L29/945 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2924/13091 ,  Y10S438/957 ,  H01L2924/014 ,  H01L2924/00

摘要： A method of fabricating a capacitor in a semiconductor substrate. The semiconductor substrate is doped to have a low resistivity. A second electrode, insulated from a first electrode, is formed over a front side surface and connected by a metal-filled via to the back side surface. The via may be omitted and the second electrode may be in electrical contact with the substrate or may be formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor is provided by a pair of oppositely-directed diodes formed in the substrate connected in parallel with the capacitor. Capacitance is increased while maintaining a low effective series resistance. Electrodes include a plurality of fingers, which are interdigitated with the fingers of other electrode. The capacitor is fabricated in a wafer-scale process with other capacitors, where capacitors are separated from each other by a dicing technique.

摘要翻译： 一种在半导体衬底中制造电容器的方法。 掺杂半导体衬底以具有低电阻率。 与第一电极绝缘的第二电极形成在前侧表面上，并且通过金属填充的通孔连接到背侧表面。 可以省略通孔，并且第二电极可以与衬底电接触，或者可以形成在介电层的顶部，从而产生一对串联电容器。 电容器的ESD保护由形成在与电容器并联连接的衬底中的一对相反方向的二极管提供。 电容增加同时保持低有效的串联电阻。 电极包括多个指状物，其与另一个电极的指状物交叉指向。 电容器采用具有其他电容器的晶片级工艺制造，其中电容器通过切割技术彼此分离。

公开(公告)号：US08614480B2

公开(公告)日：2013-12-24

申请号：US13540862

申请日：2012-07-03

申请人： Jun Wang ,  Shuming Xu ,  Jacek Korec

发明人： Jun Wang ,  Shuming Xu ,  Jacek Korec

IPC分类号： H01L29/66

CPC分类号： H01L27/0629 ,  H01L27/0727 ,  H01L29/1083 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/861

摘要： A power MOSFET is formed in a semiconductor device with a parallel combination of a shunt resistor and a diode-connected MOSFET between a gate input node of the semiconductor device and a gate of the power MOSFET. A gate of the diode-connected MOSFET is connected to the gate of the power MOSFET. Source and drain nodes of the diode-connected MOSFET are connected to a source node of the power MOSFET through diodes. The drain node of the diode-connected MOSFET is connected to the gate input node of the semiconductor device. The source node of the diode-connected MOSFET is connected to the gate of the power MOSFET. The power MOSFET and the diode-connected MOSFET are integrated into the substrate of the semiconductor device so that the diode-connected MOSFET source and drain nodes are electrically isolated from the power MOSFET source node through a pn junction.

摘要翻译： 在半导体器件的栅极输入节点和功率MOSFET的栅极之间，在半导体器件中形成并联组合的分流电阻器和二极管连接的MOSFET的功率MOSFET。 二极管连接的MOSFET的栅极连接到功率MOSFET的栅极。 二极管连接的MOSFET的源极和漏极节点通过二极管连接到功率MOSFET的源极节点。 二极管连接的MOSFET的漏极节点连接到半导体器件的栅极输入节点。 二极管连接的MOSFET的源节点连接到功率MOSFET的栅极。 功率MOSFET和二极管连接的MOSFET集成到半导体器件的衬底中，使得二极管连接的MOSFET源极和漏极节点通过pn结与功率MOSFET源节点电隔离。

公开(公告)号：US08367500B1

公开(公告)日：2013-02-05

申请号：US10378766

申请日：2003-03-03

申请人： Robert Q. Xu ,  Jacek Korec

发明人： Robert Q. Xu ,  Jacek Korec

IPC分类号： H01L21/336

CPC分类号： H01L21/76897 ,  H01L29/407 ,  H01L29/7813

摘要： A method for providing self aligned contacts for a trench power MOSFET is disclosed. The method includes, etching trenches in a substrate through a mask of silicon nitride deposited on an oxide layer, forming a gate oxide layer on the walls of the trenches, applying polysilicon to fill the trenches and to cover the surface of the mask of silicon nitride, removing the polysilicon from the surface of the mask of silicon nitride and applying a photoresist mask to cover a location of a gate bus. The method further includes recessing polysilicon plugs formed in trenches that are located in the active area to form recesses above the polysilicon plugs, filling recesses formed above the polysilicon plugs formed in trenches that are located in the active area with an insulator, applying a fourth photo resist mask to define contact windows that are opened in the nitride layer, and selectively etching the silicon nitride film and leaving flat surfaced oxide buttons covering the trenches that are located in the active area. Moreover, electric contact trenches are defined using self-aligned spacer operations, and a fifth photo resist mask is applied to pattern metal contacts that reach the semiconductor device active areas.

摘要翻译： 公开了一种用于为沟槽功率MOSFET提供自对准触点的方法。 该方法包括：通过沉积在氧化物层上的氮化硅掩模蚀刻衬底中的沟槽，在沟槽的壁上形成栅极氧化层，施加多晶硅以填充沟槽并覆盖氮化硅掩模的表面 从氮化硅掩模的表面去除多晶硅并施加光致抗蚀剂掩模以覆盖栅极总线的位置。 该方法还包括凹陷形成在沟槽中的多晶硅塞，其位于有源区域中以在多晶硅插塞之上形成凹槽，在形成于有源区域的沟槽中形成的多晶硅插塞之上形成的绝缘体填充凹陷，施加第四张照片 抗蚀剂掩模以限定在氮化物层中打开的接触窗口，并且选择性地蚀刻氮化硅膜并留下覆盖位于有源区域中的沟槽的平坦表面氧化物按钮。 此外，使用自对准间隔物操作限定电接触沟槽，并且将第五光致抗蚀剂掩模施加到到达半导体器件有源区域的图案金属接触。

公开(公告)号：US20110176247A1

公开(公告)日：2011-07-21

申请号：US13075752

申请日：2011-03-30

申请人： Haim Goldberger ,  Sik Lui ,  Jacek Korec ,  Y. Mohammed Kasem ,  Harianto Wong ,  Jack Van Den Heuvel

发明人： Haim Goldberger ,  Sik Lui ,  Jacek Korec ,  Y. Mohammed Kasem ,  Harianto Wong ,  Jack Van Den Heuvel

IPC分类号： H02H9/00 ,  H01L21/20 ,  H01L29/92

CPC分类号： H01G4/33 ,  H01G4/38 ,  H01L23/481 ,  H01L28/40 ,  H01L29/66181 ,  H01L29/945 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2924/13091 ,  Y10S438/957 ,  H01L2924/014 ,  H01L2924/00

摘要： A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor. To increase the capacitance of the capacitor while maintaining a low effective series resistance, each of the electrodes may include a plurality of fingers, which are interdigitated with the fingers of the other electrode. The capacitor is preferably fabricated in a wafer-scale process concurrently with numerous other capacitors on the wafer, and the capacitors are then separated from each other by a conventional dicing technique.

摘要翻译： 精密高频电容器包括形成在半导体衬底的前侧表面上的电介质层和位于电介质层顶部的第一电极。 半导体衬底是重掺杂的，因此具有低电阻率。 与第一电极绝缘的第二电极也形成在前侧表面上。 在一个实施例中，第二电极通过金属填充的通孔连接到衬底背面上的导电材料层。 在替代实施例中，省略通孔，并且第二电极与衬底电接触或者形成在电介质层的顶部，从而产生一对串联电容器。 电容器的ESD保护可以由形成在衬底中并与电容器并联连接的一对相反方向的二极管提供。 为了在保持低有效串联电阻的同时增加电容器的电容，每个电极可以包括与另一个电极的指状物交叉的多个指状物。 电容器优选与晶片上的许多其它电容器同时地以晶片级工艺制造，然后通过常规的切割技术将电容器彼此分离。

公开(公告)号：US07952145B2

公开(公告)日：2011-05-31

申请号：US11676618

申请日：2007-02-20

申请人： Jacek Korec ,  Stephen L. Colino

发明人： Jacek Korec ,  Stephen L. Colino

IPC分类号： H01L29/34

CPC分类号： H02J9/04 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/7835 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/3025 ,  Y10T307/461 ,  Y10T307/469 ,  Y10T307/625 ,  Y10T307/696 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate.

摘要翻译： 半导体器件包括半导体衬底，形成在半导体衬底上的第一p沟道横向扩散金属氧化物半导体（LDMOS）晶体管和形成在半导体衬底上的附加p沟道LDMOS晶体管。 第一漏极和栅电极形成在衬底上并且耦合到第一LDMOS晶体管。 另外的漏极和栅电极形成在衬底上并耦合到第二LDMOS晶体管。 用于第一和第二LDMOS晶体管的公共源电极也形成在衬底上。

公开(公告)号：US20110042742A1

公开(公告)日：2011-02-24

申请号：US12917378

申请日：2010-11-01

申请人： Anup Bhalla ,  Dorman Pitzer ,  Jacek Korec ,  Xiaorong Shi ,  Sik Lui

发明人： Anup Bhalla ,  Dorman Pitzer ,  Jacek Korec ,  Xiaorong Shi ,  Sik Lui

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/0661 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/8725 ,  H01L2924/0002 ,  Y10S257/905 ,  H01L2924/00

摘要： In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.

摘要翻译： 在沟槽栅极MIS器件中，沟槽内的栅极接触，从而不需要使栅极材料（通常为多晶硅）延伸到沟槽外部。 这避免了沟槽上角处的应力问题。 栅极金属和多晶硅之间的接触通常在位于器件的有源区域之外的栅极金属区域中形成。 描述了用于形成栅极金属和多晶硅之间的接触的各种构造，包括其中沟槽在接触区域中变宽的实施例。 由于在整个器件中多晶硅被回蚀到硅的顶表面之下，通常不需要多晶硅掩模，从而节省制造成本。