- 专利标题： Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same
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申请号： US14490581申请日： 2014-09-18
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公开(公告)号： US09768269B2公开(公告)日： 2017-09-19
- 发明人: Gilbert Dewey , Niloy Mukherjee , Matthew Metz , Jack T. Kavalieros , Nancy M. Zelick , Robert S. Chau
- 申请人： Intel Corporation
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Schwabe, Williamson & Wyatt P.C.
- 主分类号： H01L21/02
- IPC分类号： H01L21/02 ; H01L21/31 ; H01L21/469 ; H01L23/48 ; H01L29/40 ; H01L23/52 ; H01L29/51 ; H01L21/285 ; H01L23/485 ; H01L23/532 ; H01L29/49 ; H01L29/66 ; H01L29/78 ; H01L21/324 ; H01L21/768 ; H01L51/52 ; H01L31/0224 ; H01L21/04 ; H01L51/10 ; H01L51/44 ; H01L29/45 ; H01L45/00 ; H01L33/00 ; H01B1/12 ; H01L33/40
摘要：
An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.
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