- 专利标题: Vertical high voltage semiconductor apparatus and fabrication method of vertical high voltage semiconductor apparatus
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申请号: US14388745申请日: 2013-03-29
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公开(公告)号: US09722018B2公开(公告)日: 2017-08-01
- 发明人: Noriyuki Iwamuro , Shinsuke Harada , Yasuyuki Hoshi , Yuichi Harada
- 申请人: FUJI ELECTRIC CO., LTD. , NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
- 申请人地址: JP Kawasaki-shi JP Tokyo
- 专利权人: FUJI ELECTRIC CO., LTD.,NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
- 当前专利权人: FUJI ELECTRIC CO., LTD.,NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
- 当前专利权人地址: JP Kawasaki-shi JP Tokyo
- 代理机构: Westerman, Hattori, Daniels & Adrian, LLP
- 优先权: JP2012-081580 20120330
- 国际申请: PCT/JP2013/059777 WO 20130329
- 国际公布: WO2013/147276 WO 20131003
- 主分类号: H01L29/15
- IPC分类号: H01L29/15 ; H01L29/06 ; H01L29/66 ; H01L29/739 ; H01L29/78 ; H01L29/10 ; H01L29/16 ; H01L29/04
摘要:
A silicon carbide vertical MOSFET includes an N-counter layer of a first conductivity type formed in a surface layer other than a second semiconductor layer base layer selectively formed in a low concentration layer on a surface of the substrate, a gate electrode layer formed through a gate insulating film in at least a portion of an exposed portion of a surface of a third semiconductor layer of a second conductivity type between a source region of the first conductivity type and the N-counter layer of the first conductivity type, and a source electrode in contact commonly with surfaces of the source region and the third semiconductor layer. Portions of the second conductivity type semiconductor layer are connected with each other in a region beneath the N-counter layer.
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