- 专利标题: ELECTRONIC DEVICE FABRICATION USING AREA-SELECTIVE DEPOSITION
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申请号: US18109365申请日: 2023-02-14
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公开(公告)号: US20240282632A1公开(公告)日: 2024-08-22
- 发明人: Zachary J. Devereaux , Bhaskar Jyoti Bhuyan , Thomas Joseph Knisley , Zeqing Shen , Susmit Singha Roy , Mark J. Saly , Abhijit Basu Mallick
- 申请人: Applied Materials, Inc.
- 申请人地址: US CA Santa Clara
- 专利权人: Applied Materials, Inc.
- 当前专利权人: Applied Materials, Inc.
- 当前专利权人地址: US CA Santa Clara
- 主分类号: H01L21/768
- IPC分类号: H01L21/768 ; C23C16/04 ; C23C16/32 ; C23C16/40 ; C23C16/455 ; H01L21/02
摘要:
A method includes selectively forming at least one passivation layer on at least one first conductive layer disposed in a first interlevel dielectric (ILD) layer, selectively forming at least one catalyst layer on the at least one passivation layer, wherein the at least one passivation layer prevents formation of the at least one catalyst layer on the first conductive layer, and selectively forming at least one supplemental dielectric layer using the at least one catalyst layer. The at least one catalyst layer induces formation of the at least one supplemental dielectric layer, and the at least one supplemental dielectric layer includes a dielectric material having a dielectric constant of less than or equal to about 4.
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