- 专利标题: Transistors with metal source and drain contacts including a Heusler alloy
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申请号: US16306540申请日: 2016-07-01
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公开(公告)号: US11107908B2公开(公告)日: 2021-08-31
- 发明人: Sasikanth Manipatruni , Anurag Chaudhry , Dmitri E. Nikonov , Jasmeet S. Chawla , Christopher J. Wiegand , Kanwaljit Singh , Uygar E. Avci , Ian A. Young
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Schwabe, Williamson & Wyatt, P.C.
- 国际申请: PCT/US2016/040877 WO 20160701
- 国际公布: WO2018/004700 WO 20180104
- 主分类号: H01L29/66
- IPC分类号: H01L29/66 ; H01L29/45 ; H01L29/775 ; H01L29/10 ; H01L29/739 ; H01L29/06 ; B82Y10/00 ; H01L29/786 ; H01L29/423 ; H01L29/417 ; H01L21/285 ; H01L29/16 ; H01L29/20 ; H01L29/24 ; H01L29/47 ; H01L29/78
摘要:
Embodiments herein describe techniques for a semi-conductor device comprising a channel having a first semiconductor material; a source contact coupled to the channel, comprising a first Heusler alloy; and a drain contact coupled to the channel, comprising a second Heusler alloy. The first Heusler alloy is lattice-matched to the first semiconductor material within a first predetermined threshold. A first Schottky barrier between the channel and the source contact, and a second Schottky barrier between the channel and the drain contact are negative, or smaller than another predetermined threshold. The source contact and the drain contact can be applied to a strained silicon transistor, an III-V transistor, a tunnel field-effect transistor, a dichalcogenide (MX2) transistor, and a junctionless nanowire transistor.
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