US10911180B2
A method for data integrity check in a network device of a computer network. The network device includes a communication module and a monitoring module. The monitoring module receives (a) the same data being received by a communication module from an input port of the network device, and (b) the same data the communication module transmits towards output port/s of the network device. The monitoring module (i) derives, after receiving the same R-data as the communication module, a sub-tuple of the R-data, a “R-data sub-tuple”, wherein the R-data sub-tuple includes m of the n data elements of the n-tuple of R-data, wherein m>0 and m
US10911178B2
Systems and methods for blind detection of a numerology of a received signal are described. In one aspect, a method is provided for a user equipment (UE) to blindly detect the numerology of a received signal. The method includes correlating cyclic prefix (CP) signals in the received signal in the time domain based on a plurality of hypotheses of subcarrier spacing (SCS) and determining a numerology of the received signal for a corresponding hypothesis of SCS of the plurality of hypotheses based on the correlated CP signals.
US10911172B2
A user apparatus, in a radio communication system including a plurality of base stations, including a reception unit configured to receive, from a connecting base station, control information to be used for reducing an interference signal sent from an interference base station for the user apparatus; and an interference reducing unit configured to reduce the interference signal by using the control information to obtain a desired signal sent from the connecting base station.
US10911166B2
This disclosure relates to a communication technique that fuses a 5G communication system for supporting a higher data transfer rate than 4G systems, with IoT technology, and a system therefor. This disclosure can be applied to intelligent services (for example, smart home, smart building, smart city, smart car, or connected car, health care, digital education, retail, security, and safety-related services or the like) on the basis of 5G communication technology and IoT related technology. A method for a terminal according to the present invention comprises the steps of: receiving setting information for a reference signal; confirming whether beam switching is possible in a resource area to which the reference signal is to be transmitted; and measuring the reference signal based on the confirmation result.
US10911165B1
In accordance with an embodiment, a method includes: receiving, by an adjustable frequency doubling circuit, a first clock signal having a first clock frequency; using the adjustable frequency doubling circuit, generating a second clock signal having a second clock frequency that is twice the first clock frequency; measuring a duty cycle parameter of the second clock signal, where the duty cycle parameter is dependent on a duty cycle of the first clock signal or a duty cycle of the second clock signal; and using the adjustable frequency doubling circuit, adjusting the duty cycle of the first clock signal or the second clock signal based on the measuring.
US10911164B2
The present disclosure provides apparatus and methods for the calibration of analog circuitry on an integrated circuit. One embodiment relates to a method of calibrating analog circuitry within an integrated circuit. A microcontroller that is embedded in the integrated circuit is booted up. A reset control signal is sent to reset an analog circuit in the integrated circuit, and a response signal for the analog circuit is monitored by the microcontroller. Based on the response signal, a calibration parameter for the analog circuit is determined, and the analog circuit is 10 configured using the calibration parameter. Other embodiments, aspects and features are also disclosed.
US10911158B2
A method and system of high speed radio frequency communication between an outside of a metallic pipeline or vessel and an interior volume contained by the metallic pipeline or vessel includes passing a high speed radio frequency signal through a communication portal having a high speed radio frequency permittive material exposed to the interior volume of the metallic pipeline and to the outside. The high speed radio frequency signal may be transmitted from the interior volume to the outside or from the outside to the interior volume. The communication portal may be a cylindrical- or planar-shaped body connected to the metallic pipeline. A tool located within the interior volume may transmit, receive, or transmit and receive the high speed radio frequency signal. The high speed radio frequency signal may be configured according to a 2.45 GHz standard protocol.
US10911148B2
An optical transmission apparatus includes first and second optical waveguides to transmit light of multiple wavelengths; optical couplers on the waveguides, to couple the lights transmitted through the waveguides, so as to output the coupled light to the waveguides; phase shifters provided at preceding stages of part of the optical couplers, to change a phase shift amount of the light transmitted through the first and/or second optical waveguides, wherein the number of optical couplers in the part is greater than or equal to the number of the types of wavelengths; a monitor to monitor the intensity of the light output to the second optical waveguide via the optical coupler at the last stage; and a controller to control the phase shifters by changing the phase shift amount for each of the phase shifters in a direction in which the output of the monitor decreases.
US10911147B2
A system for data transmission has a transmitter and a receiver connected by an optical channel. The transmitter has a transmitter laser and a transmitter-side electroabsorption modulator with an optical output. An electrical data input of the transmitter is connected to an electrical modulation terminal of the transmitter-side electroabsorption modulator. The receiver has a receiver laser and a receiver-side electroabsorption modulator with an optical output forming the input of the receiver. An electrical data output of the receiver is connected to the electrical modulation terminal of the receiver-side electroabsorption modulator. The transmitter and receiver lasers are detunable by specification of a physical variable, each provided by a respective control unit. The control units are synchronized and they specify the same signal at their outputs for establishing the physical variable for establishing the laser frequency.
US10911145B2
In an aspect, an apparatus for distribution of frequency reference to a receiving end over a transmission medium comprises a first mixer adapted to mix a frequency reference signal having a reference frequency with a local oscillator signal having a local oscillator frequency to provide a forward frequency reference signal, a communication section adapted to transmit the forward frequency reference signal and receive a first backward frequency reference signal, a second mixer adapted to mix the first backward frequency reference signal with the local oscillator signal to provide a second backward frequency reference signal and a phase comparator and control circuit adapted to adjust the local oscillator frequency based on a phase shift of the second backward frequency reference signal so as to compensate for a phase shift of the forward frequency reference signal.
US10911141B1
A system for transmitting data over an optical communication path is configured to receive data to be encoded in a bitstream for transmission using an optical communication path and encodes the received data to obtain a bitstream. The system is further configured to determine that the bitstream includes a sequence of consecutive bits, and obtain a power level at which to transmit a portion of the bitstream based on a count of the consecutive bits in the sequence. The system may be configured to selectively activate a light source at a power level according to a modulation scheme to optically transmit the portion of the bitstream at the power level.
US10911138B2
The invention relaxes to a replacement scheduling method and system for ultra-low loss optical fibers in a backbone network, which are designed to improve spectrum, utilization efficiency. The method includes: S1: calculating a gam respectively after each optical fiber link is replaced, that is, calculating a product of multiplying a quantity of frequency slots (FSs) reduced after each optical fiber link is replaced by a remaining time for finishing replacing all the remaining optical fiber links; S2: selecting an optical fiber link having the highest gain after the optical fiber link is replaced to perform replacement; and repeating S1 and S2 until all the optical fiber links that need to be replaced have been replaced. In the present invention, a replacement order of optical fibers is arranged most appropriately, so as to save as many as spectrum resources for operators for use by additional services. (FIG. 2)
US10911135B2
A computer system is provided that includes devices configured to acquire input data. The system further includes a remote node (RN) configured to receive a first packet from a control node (CN). The first packet includes a packet header including a master timestamp, first control data and a CRC. The RN is also configured to verify integrity of the first control data based on the received CRC, generate and transmit to the CN a second packet. The second packet includes a packet header which includes a remote timestamp. The system also includes a CN connected with the RN via high-speed serial interfaces. The CN is configured to receive the second packet, determine status of the first packet based on the control data included in the second packet and configured to retransmit the first packet or generate and transmit a third packet based on the determined status of the first packet.
US10911132B2
The present invention relates to low earth orbit satellites for air traffic control. One or more LEO satellites serves as a link between a control tower and an aircraft. The one or more LEO satellites are adapted for a) receiving an Automatic Dependent Surveillance-Broadcast, ADS-B, signal from an aircraft; b) receiving and/or transmitting a signal from/to a control tower; and c) receiving and/or transmitting a VHF signal from/to an aircraft.
US10911131B1
A hybrid relay for high density venues may be provided. First, a user density value at an Access Point (AP) disposed above a ground level may be determined. Then a user density value at an AP-relay disposed at the ground level may be determined. Next, it may be determined that a difference between the user density value at the AP and the user density value at the AP-relay is greater than a predetermined threshold. The AP-relay may then be switched from a sensor mode to an AP-relay mode in response to determining that the difference between the user density value at the AP and the user density value at the AP-relay is greater than the predetermined threshold.
US10911125B2
One example method includes receiving, by a terminal, indication information sent by a base station, where the indication information indicates a precoding matrix in a first precoding matrix set and a transmission rank corresponding to the precoding matrix, and the precoding matrix is used to precode transmit data streams at r transmission layers to obtain signals to be sent on N transmission ports of the terminal; and when r>1, a nonscalar part of a precoding matrix whose transmission rank is r in the first precoding matrix set is obtained by combining columns in nonscalar parts of r precoding matrices, and the r precoding matrices are precoding matrices selected from all precoding matrices whose transmission ranks are 1; and determining, by the terminal based on the indication information, the precoding matrix for precoding the transmit data streams.
US10911122B2
This application provides a reference signal sending method, a reference signal receiving method, a network device, and a terminal device, to perform CSI (Channel State Information) measurement by using more precoding vectors (or precoding matrices), to measure more equivalent channels, thereby improving flexibility and a spatial degree of freedom of network device scheduling. The method includes: performing, by the network device, precoder cycling on a first reference signal by using at least two precoding vectors, to obtain a precoded first reference signal, where the precoded first reference signal is borne in a plurality of physical resource groups, and signals borne in any two adjacent physical resource groups correspond to different precoding vectors; and sending, by the network device, the precoded first reference signal to the terminal device by using the plurality of physical resource groups, where the first reference signal is used by the terminal device to perform CSI measurement.
US10911120B2
Certain aspects relate to methods and apparatus for wireless communication. The apparatus generally includes a first interface configured to output one first frame for transmission to solicit CSI feedback from each of one or more first wireless nodes associated with a first BSS and from each of one or more second wireless nodes associated with a second BSS, a second interface configured to obtain the CSI feedback solicited from the first and second wireless nodes, and a processing system configured to generate data frames for the first wireless nodes based on the CSI feedback solicited from the first wireless nodes, and one or more nulling frames based on the CSI feedback solicited from the second wireless nodes. The first interface is configured to simultaneously output the data frames for beamformed transmission to the first wireless nodes, and the nulling frames for beamformed transmission to the second wireless nodes.
US10911113B2
A communication system and a codec method based on deep learning and known channel state information (CSI) are provided. The communication system includes: a first electronic apparatus including a known first link CSI and a CSI encoder having a deep learning function; and a second electronic apparatus including a known second link CSI and a CSI decoder having a deep learning function. The first and second link CSIs have a correlation or a similarity. The CSI encoder of the first electronic apparatus encodes or compresses the first link CSI into the first codeword, and feeds the first codeword back to the second electronic apparatus via a feedback link. The CSI decoder of the second electronic apparatus encodes or compresses the second link CSI into a second codeword, and decodes or restores the first link CSI of the first electronic apparatus based on the first codeword and the second codeword.
US10911110B2
A method and an apparatus for transmitting and receiving channel state information in a multi-antenna wireless communication system are disclosed. Specifically, a method for reporting channel state information (CSI), by a User Equipment (UE), in a multi-antenna wireless communication system, the method comprising receiving, from a base station, configuration information for single CSI reporting in which a non-precoded CSI-RS based CSI reporting and a beamformed CSI-RS based CSI reporting are combined, reporting a first Precoding Matrix Indicator (PMI) and/or a first Rank Indicator (RI) derived based on a non-precoded CSI-RS to the base station, and reporting a Channel Quality Indicator (CQI), a second PMI, and a second RI based on a beamformed CSI-RS to the base station, wherein a value of the first RI is determined as only a value belonging to a previously determined set.
US10911103B2
Disclosed herein is a portable electronic device for facilitating a proximity based interaction with a short range communication enabled object. Further, the portable electronic device may include a transceiver configured for transmitting a transmitted short range communication signal and receiving a received short range communication signal. Further, the portable electronic device may include a processor communicatively coupled to the transceiver, configured for detecting a proximity based event based on receiving the received short range communication signal from the short range communication enabled object, analyzing the received short range communication signal based on the detecting of the proximity based event, determining a second object identifier associated with the short range communication enabled object based on the analyzing, and performing a predetermined action based on the second object identifier. Further, the portable electronic device may include a memory device configured for storing a first digital asset and a first object identifier associated with the first digital asset.
US10911100B2
An electronic device is provided. The electronic device includes a first sensor configured to obtain an electromagnetic (EM) signal from an external device, a first communication module configured to provide a magnetic stripe transmission (MST) signal, a processor, and a memory coupled with the processor, wherein the memory is configured to store instructions which, upon execution, instruct the processor to control the first communication module to transmit, to the external device, the MST signal which is predetermined corresponding to the external device based on the obtained EM signal.
US10911069B2
Disclosed herein are memory devices, systems, and methods of content-aware decoding of encoded data. In one aspect, an encoded data chunk is received and one or more characteristics, such as source statistics, are determined. A similar data chunk (that may, e.g., contain data of a similar type) with comparable statistics may be sought. The similar data chunk may, for example, have source statistics that are positively correlated to the source statistics of the encoded data chunk to be decoded. Decoder parameters for the encoded data may be set to correspond with decoder parameters suited to the similar data chunk. The encoded data chunk is decoded using the new decoder parameters. Decoding encoded data based on content can enhance performance, reducing decoding latency and/or power consumption.
US10911064B1
Methods, apparatuses, and computer-readable media for compressing data for storage or transmission. Input data is compressed in a first stage utilizing a first compression algorithm and the frequencies of occurrence of symbols and symbol pairs in the output from the first stage is calculated. The output from the first stage is then encoded to a final compressed bit string in a second stage utilizing a second compression algorithm based on the calculated frequencies of occurrence of the symbols and the symbol pairs.
US10911063B2
Examples herein relate to decoding tokens using speculative decoding operations to decode tokens at an offset from a token decoded by a sequential decoding operation. At a checkpoint, a determination is made as to whether tokens to be decoded by the sequential and speculative decoding operations align. If there is alignment, the speculatively decoded tokens after a discard window are committed and made available for access. If there is not alignment, the speculatively decoded tokens are discarded. A miss in alignment and a fullness level of a buffer that stores speculatively decoded tokens are assessed to determine a next offset level for a start of speculative decoding. A size of a discard window can be set using a relationship based on the offset level to improve buffer utilization and to attempt to improve changes of alignments.
US10911056B2
A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
US10911055B1
An oscillator assembly includes a scribe seal, an oscillator circuit, and a calibration circuit. The oscillator circuit includes an output. The calibration circuit is coupled to the oscillator circuit. The calibration circuit includes a reference frequency terminal, a conductor coupled to the reference frequency terminal, and an oscillator input terminal. The conductor extends to an edge of the oscillator circuit assembly and penetrates the scribe seal. The oscillator input terminal is coupled to the output of the oscillator circuit.
US10911052B2
A system for retiming a multi-level signal that forms an eye diagram when plotted, such as a PAM4 signal that includes an equalizer configured to create an equalized signal and a first amplifier configured to amplify the equalized signal, responsive to a first amplifier control signal, to create a first amplified signal, and a second amplifier configured to amplify the equalized signal, responsive to a second amplifier control signal, to create a second amplified signal. An eye monitor processes the equalized signal, the first amplified signal, and the second amplified signal to create a first retiming clock phase signal and a second retiming clock phase signal, which control sampling times for flip-flops. One or more delays and one or more emphasis modules are configured to delay and introduce emphasis into an output from the flip-flops, the resulting signals are combined in a summing junction to create the retimed signal.
US10911049B2
Methods, systems, and devices for shifting voltage levels of electrical signals and more specifically for boosted high-speed level shifting are described. A boosted level shifter may include a driver circuit that generates a drive signal having a greater voltage swing than an input signal, and the drive signal may drive the gate of a pull-up transistor within the boosted level shifter. The lower bound of the drive signal may in some cases be a negative voltage. Driving the pull-up transistor with a drive signal having a greater voltage swing than the input signal may improve the operational speed and current-sourcing capability of the pull-up transistor, which may provide speed and efficiency benefits.
US10911045B1
A segmented direct gate drive circuit of a depletion mode GaN power device, a gate voltage of the GaN power device is charged from a negative voltage turn-off level to a threshold voltage of the GaN power device; when the gate voltage of the GaN power device is charged to the threshold voltage of the GaN power device, a current mirror charging module first turns on less than N of charging current mirror modules to charge the gate voltage of the GaN power device from the threshold voltage of the GaN power device to a Miller platform voltage of the GaN power device, and turns on N charging current mirror modules to charge the gate voltage of the GaN power device from the Miller platform voltage of the GaN power device to a zero level.
US10911044B1
An output circuit receives a data signal biased within a first voltage range associated with a first power supply voltage and generates an output signal on an output node biased within a second voltage range in response to the data signal, the second voltage range is associated with a second power supply voltage greater than the first power supply voltage. The output circuit generates pull-up and pull-down signals that are within the first voltage range in response to the data signal. The output circuit includes an output driver circuit including a pull-up circuit and a pull-down circuit. The pull-up circuit, when activated, generates the output signal indicative of the second power supply voltage in response to a modified pull-up signal being the pull-up signal level-shifted to a third voltage range. The pull-down circuit, when activated, generates the output signal being the ground potential in response to the pull-down signal.
US10911043B2
A device and a method for switching over a semiconductor switch with a switching signal acting on a control connection of the semiconductor switch, the switching signal being switched over as a response to registering a switchover of an activation signal; a down time being ascertained between the start of the switchover of the switching signal and the switchover of the semiconductor switch; the switchover of the semiconductor switch being delayed by a waiting period, for example by delaying the output of the switching signal and/or changing the signal level, so that an actual switching time, corresponding to a setpoint switching time, between the registration of the switchover of the activation signal and the switchover of the semiconductor switch is obtained.
US10911041B2
An electronic circuit module is provided. The electronic circuit module prevents damage by efficiently detecting an overcurrent in the electronic circuit module using an SiC MOSFET. The electronic circuit module includes an input unit that is configured to input a reference voltage and a switching unit that is configured to output a first voltage based on a current flow. A converter is configured to output a second voltage based on the first voltage and the reference voltage. An output unit is configured to compare a magnitude of the reference voltage with a magnitude of the second voltage to output a feedback signal when the second voltage is greater than the reference voltage.
US10911040B2
High power radio frequency (RF) switches with low leakage current and low insertion loss are provided. In one embodiment, an RF switch includes a plurality of transistors and is configured to selectively connect one of a transmit path or a receive path to an antenna. All of the transistors are configured to be in an on state when the RF switch operates in a high power mode and all of the transistors are configured to be in an off state when the RF switch operates in a low power mode.
US10911038B1
A network flow processor integrated circuit includes a plurality of processors, a plurality of multi-threaded transactional memories (MTMs), and a configurable mesh posted transaction data bus. The configurable mesh posted transaction data bus includes a configurable command mesh and a configurable data mesh. Each of these configurable meshes includes crossbar switches and interconnecting links. A command bus transaction value issued by a processor can pass across the command mesh to an MTM. The command bus transaction bus value includes a reference value. The MTM uses the reference value to pull data across the configurable data mesh into the MTM. The MTM then uses the data to carry out the commanded transactional memory operation. Multiple such commands can pass across the posted transaction bus across different parts of the integrated circuit at the same time, and a single MTM can be carrying out multiple such operations at the same time.
US10911035B1
A fixed-width pulse generator includes a metastability detector circuit, a delay signal generator, and a combinational logic circuit. The metastability detector circuit is configured to receive a trigger signal and generate state detection signals. The delay signal generator is configured to receive the state detection signals and the trigger signal, and delay the trigger signal by two different delay values to generate two different delayed signals. One of the delay values is based on the state detection signals. The combinational logic circuit is configured to receive the two delayed signals and an error signal, and generate a fixed-width pulse that remains constant over process, voltage, and temperature variations.
US10911028B1
A device for phase adjustment preset for an N-path filter comprising a logic block; a ring divider array creating a local oscillator drive for a mixer; the ring divider array comprising: a plurality of registers, each comprising: inputs S, R, D, and clock, and output Q; the plurality of registers comprising at least: a first register; a second register; and an Nth register; a preset control word; wherein the preset control word is applied to the logic block, the logic block providing input to each of the S and the R inputs of each the register; whereby a desired starting phase of the divider is controlled. A method includes defining a desired starting conditions; determining a control word from desired starting conditions; applying control word to logic block; applying a reset signal to logic block; and outputting values for each of S and R to each register.
US10911015B2
Systems, devices, and methods for tunable filters that are configured to support multiple frequency bands, such as within the field of cellular radio communication, can include a first resonator and a second resonator configured to block signals within one or more frequency ranges, and one or more coupling element connected to both the first resonator and the second resonator. The one or more coupling element can be configured to provide low insertion loss within a pass band.
US10911011B2
A coherent optical modem includes one or more inputs; one or more amplifier circuits, each coupled to a respective input of the one or more inputs; and one or more receiver circuits each including an analog-to-digital converter, each coupled to a respective amplifier circuit of the one or more amplifier circuits; wherein the one or more amplifier circuits are configured to implement an automatic gain control loop to provide a constant signal amplitude at an input of the analog-to-digital converter of a respective receiver circuit.
US10910993B2
The invention relates to circuit arrangements for reducing potential-induced degradation in photovoltaic modules of a photovoltaic generator, said circuit arrangements comprising an insulation monitoring device for a temporally continuous insulation monitoring of the photovoltaic generator. Furthermore, the invention relates to a photovoltaic system comprising a circuit arrangement for reducing potential-induced degradation in photovoltaic modules, said photovoltaic system comprising a photovoltaic generator and an insulation monitoring device for a temporally continuous insulation monitoring of the photovoltaic generator. Different solutions are proposed which enable reducing potential-induced degradation while simultaneously continuously monitoring insulations. The circuit arrangements according to the invention rest upon an insulation monitoring device interacting with measures based circuit technology for influencing potentials in a photovoltaic module.
US10910991B2
A solar window system for a building includes multiple heat generation encasements each including thermoelectric sheets, where the thermoelectric sheets are positioned inside a housing having an interior metal layer. Air inside each heat generation encasement is heated by solar energy. Inside each heat generation encasement, there are pipes filled with Phase-Change Material (PCM) materials that help provide heating to the building. The solar window system further includes a storage tank on top of the system filled with PCM materials for storing heat from the heated air, the storage tank being connected to the pipes of each heat generation encasement. The solar window system includes a set of connection pipes, wherein the set of connection pipes draw cold air from an indoor space inside the building into the plurality of heat generation encasements, connect each of the heat generation encasements to at least two other heat generation encasements, and transfer the heated air from the set of heat generation encasements to the storage tank. The solar window system also includes circular movable rings that can be open and closed as needed. These rings are located around each heat generation encasement and have two movable flexible solar panels capable of generating electricity.
US10910990B2
The present invention relates to a solar cell module, includes a plurality of solar cells, a concentration unit having a flat surface to which solar light is incident, arranged at a position spaced apart from the solar cells, and configured to concentrate the incident solar light for output, and a reflection unit configured to reflect light between the solar cells, wherein the concentration unit is provided with a reflective region such that solar light concentrated by the concentration unit and output from is trapped between the concentration unit and the reflection unit, and an air gap is formed between the concentration unit and the reflection unit.
US10910988B2
A method to make an ultra-stable structural laminate of a cementitious material with a nano-molecular veneer and a foam component catalytically reacted into an expanded closed cell foam having a thickness from ⅛th inch to 8 inches, a density from 1.5 pounds/cubic foot to 3 pounds/cubic foot that inter-engages the cementitious material forming a matrix creating the ultra-stable structural laminate with fire resistance; a lateral nail pull strength from 44 pounds to 300 pounds of force; an insulation R value from 1 to 40; a resistance to seismic impact for earthquakes over 3.1 on the Richter Scale; a break point from 7 lbs/inch to 100 lbs/inch; and a resistance to wind shear equivalent to a 15 mph downburst.
US10910981B2
An electric power conversion system includes: an inverter; a voltage converter including a high-voltage end connected to a direct-current power source and a low-voltage end connected to the inverter; and a controller. The controller is configured to control switching elements such that a voltage of the low-voltage end becomes lower than a voltage of the high-voltage end in a first state. The controller is configured to control the switching elements such that the voltage of the low-voltage end becomes equal to the voltage of the high-voltage end in a second state.
US10910978B2
A low cost and efficient method and apparatus for calibrating high performance internal permanent magnet motors that involves starting from an initial estimation of the rotor position and improving the estimation incrementally by successively commanding various current vectors and making adjustments to the estimated initial position according to the rotor's physical reaction to such current vectors.
US10910977B2
The present invention relates to a method for determining a state of a bearing of a three phase electric machine, the electric machine having a rotor, which is supported by the bearing, the electric machine being connected to a three phase inverter for supplying the electric machine with electric power, the three phase inverter being controlled to apply a pulse width modulation with a predefined scheme to create three phase currents, the method comprises: —determining a first phase current provided to the electric machine; —determining a second phase current provided to the electric machine, the second phase current being different to the first phase current; —determining the power spectral density of the park's vector based on the first phase current and the second phase current; —determining an amplitude of the power at a predefined frequency of the power spectral density, wherein the predefined frequency depends on the rotational speed of the rotor and the scheme of the pulse width modulation; —comparing the amplitude of the power at the predefined frequency with a predefined power value; and—determining, based on the comparison, whether a failure of the bearing has occurred or the bearing is degraded.
US10910974B2
A feedback control switching unit of an inverter control unit selects, based on a magnitude relationship between a predetermined switching determination amount and at least one switching threshold, at least one of feedback control units to thereby execute switching among feedback control modes, such as a current feedback control mode and a torque feedback control mode, of the respective feedback control units for driving of the AC motor. A switching command generating unit generates a switching command for an inverter based on a manipulated variable calculated by the selected feedback control unit. When a torque response request determining unit determines that a required torque responsiveness is high, the feedback control switching unit reduces the number of executions of switching among the feedback control modes.
US10910963B2
A power stealing system having an electrical load, a capacitive element having an input connected to the electrical load. Some power from the electrical load may go through the capacitive element to an input of a rectifier. A voltage regulator may have an input connected to an output of the rectifier to set and control a voltage level of the electrical power from the rectifier, and provide an output of power stolen from the electrical load. An amount of power flowing through the capacitive element may be less than one percent of power flowing through the electrical load.
US10910962B2
A power generation system includes a plurality of energy conversion devices for generating a plurality of power signals based on one or more sensed environmental conditions. The system further includes a plurality of power conditioning circuits each coupled to one or more of the energy conversion devices for receiving the power signals and storing energy in an energy storage system. The system also includes a selection circuit coupled to at least one of the power conditioning circuits and receiving a first input power signal from one of the power conditioning circuits and a second input power signal. The selection circuit is configured to deliver an output power signal representing a selection from between the first and second input power signals based on a relative voltage level of the first and second input power signals. A method of power generation, and associated power module, are also disclosed.
US10910952B1
Embodiments of this disclosure provide a control apparatus and method for a current resonance circuit and a current resonance power supply. The control method includes: performing integration on a resonance current of the current resonance circuit or a switching current of one or more switching elements to generate an integration signal; generating a feedback signal of the current resonance circuit; comparing the integration signal with the feedback signal, and generating a measurement signal according to a comparison result; performing digital filtering on the measurement signal; and according to the measurement signal after filtering, generating a pulse width modulation signal controlling the switching elements.
US10910948B2
A controller for a switched mode power supply (SMPS) including a reference voltage signal generator to generate a variable reference voltage signal for regulating an output voltage of the SMPS, and a voltage droop control signal generator to receive a current indicator signal indicative of an output current of the SMPS, and generate an output voltage droop control signal in response to a first function and a second function of the current indicator signal. The first function is employed when the reference voltage signal generator ramps the variable reference voltage signal, and the second function is employed thereafter. The controller includes a switching control signal generator to receive a voltage indicator signal, and to generate a control signal to regulate the output voltage of the SMPS based on the voltage indicator signal, the variable reference voltage signal, and the output voltage droop control signal.
US10910940B2
An apparatus includes a voltage regulator including a high-side field-effect transistor, a low-side field-effect transistor, an inductor, and a conductive net connecting the high-side field-effect transistor, the low-side field-effect transistor and the inductor. The apparatus further includes an attenuation circuit coupled to the conductive net, wherein the attenuation circuit includes an electronic switch that enables and disables an amount of attenuation provided by the attenuation circuit. Examples of the attenuation circuit include a snubber circuit and a boost resistor circuit.
US10910939B2
An inverter device according to an embodiment includes a plurality of switching elements and processing circuitry. The switching elements are connected to each other in parallel, and each of them includes a transistor and a free wheeling diode connected to the transistor in antiparallel. The processing circuitry is configured to monitor a current flowing through the free wheeling diode included in each switching element or a temperature of the free wheeling diode and to control, in accordance with the current or the temperature, a load on each free wheeling diode to prevent unbalance of loads between free wheeling diodes in the switching elements.
US10910935B2
A linear actuator comprising a first fixed portion comprising a linear array of stator teeth, each surrounded by one or more turns of electrical wire, a controller which generates a set of currents that are applied to phase windings of the first fixed portion to generate a pattern of magnetic poles along the array of stator teeth, a spacing between the magnetic poles being larger than a spacing between adjacent stator teeth of the first fixed portion, a second fixed portion that comprises an alternating set of magnet poles, a spacing between adjacent poles being smaller than the spacing of the magnetic poles of the first fixed portion created by the controller, and a movable output portion that comprises a linear array of pole pieces that extend along a length of the moveable output portion that is greater than a stroke length of the actuator and longer than a length of the fixed portion, whereby in use a length of the movable output portion is at all times located between the first and second fixed portions, in which the pole pieces that are located between the first and second fixed portions shape a magnetic flux acting between the magnetic poles of the first fixed portion and the magnet poles of the second fixed portion, and whereby in use the controller is arranged to cause linear movement of the moveable output portion by moving the magnetic poles of the first fixed portion along the first array.
US10910923B2
The present invention provides a rotating electric machine and a method of detecting electric discharge (a defect detection method for a rotating electric machine), which are able to early detect vibration sparking between a stator winding and a stator core. A rotating electric machine of the present invention comprises a cylindrical stator including a stator core and a stator winding, a rotor disposed inside the stator, at least one key bar disposed on an outer periphery of the stator core and extended in an axial direction of the stator, and at least one current detector disposed on the key bar and configured to measure a current flowing in the key bar.
US10910914B2
An electric power tool includes a driving unit generating a driving force by electricity and various components functioning by electricity, a circuit board on which a control unit configured to control the driving unit and the various components is mounted, a plurality of connectors connecting a plurality of wirings, which extend from the driving unit and the various components, with a plurality of wirings, which extend from the circuit board, a body portion installed therein with the driving unit, the various components, the circuit board and the plurality of connectors, and a receiving portion which receives the plurality of connectors therein and which is fixed to the body portion.
US10910913B2
An object of the present invention is to provide a mechanism for disengaging a hub from an output shaft of a motor, which is convenient to propel the scooter/wheelchair manually. For this purpose, the present invention employs the following technical solution. The present invention discloses a mechanism for disengaging a hub from an output shaft of a motor; an output end of the output shaft is extended out of the motor; a coupling is fixedly sheathed on the output end of the output shaft; a hub, a movable sleeve and a compression spring are sheathed on the coupling; a stopper is fixed at an end of the output end of the output shaft; the compression spring is limited between the stopper and the movable sleeve; the hub has a central hub hole by which the hub is sheathed on the coupling; a plurality of first positioning grooves, which are arranged circularly and uniformly spaced apart from each other, are formed on an inner edge of the hub; a coupling bulge is provided in the circumference of the coupling, and a plurality of second positioning grooves, which are arranged circularly and uniformly spaced apart from each other, are formed on the coupling bulge; a plurality of first positioning bulges, which are arranged circularly and uniformly spaced apart from each other, are provided on the movable sleeve.
US10910910B2
A drive motor for a laundry appliance includes a stator having a plurality of windings that extend around teeth of the stator. A rotor is in electromagnetic communication with the stator. The rotor is coupled to a drive shaft that extends through the stator. When the winding of the stator is electrically energized, the rotor rotates relative to the stator at a predetermined range of rotational frequencies that includes a baseline natural frequency of the rotor. A harmonic-modulating member is attached to the rotor that modulates the baseline natural frequency of the rotor to be a modulated natural frequency. The predetermined range of rotational frequencies is free of the modulated natural frequency of the rotor.
US10910908B2
A motor includes a base, a stator, a dynamic pressure bearing unit and a rotor. The base includes a shaft tube. The shaft tube includes a closed end and an open end. The stator is mounted around the shaft tube. The dynamic pressure bearing unit includes a bearing, a dynamic pressure assembly and a thrust plate. The bearing is received in the shaft tube. The dynamic pressure assembly and the thrust plate are disposed in a position relatively adjacent to the open end of the shaft tube and relatively distant from the closed end of the shaft tube. The dynamic pressure assembly is located between the bearing and the thrust plate. A lubricating fluid layer is disposed between the dynamic pressure assembly and the thrust plate. The rotor is connected to the thrust plate and is rotatably coupled with the bearing.
US10910907B2
A motor includes a shaft, a bearing that rotatably supports the shaft, and a hub fixed to the shaft. The shaft includes a first shaft portion extending in an axial direction, a second shaft portion projecting axially upward from an axially upper end surface of the first shaft portion and including a diameter smaller than that of the first shaft portion, and a screw hole recessed axially downward from the axially upper end surface. The hub includes a shaft fixing hole into and in which the second shaft portion is inserted and fixed. An outer surface of the second shaft portion includes a first region, and a second region axially above the first region, and including surface roughness smaller than that of the first region.
US10910903B2
A coreless electromagnetic machine includes a dual rotor and a stator. The dual rotor is adapted to rotate about an axis, and includes inner and outer rotor segments. The outer rotor segment is spaced radially outward from, and axially aligned to, the inner rotor segment. The inner and outer rotor segments radially define an annular chamber. The stator is disposed, at least in-part, in the annular chamber.
US10910900B2
A coil (3) for a rotary electric machine (3) is constituted by eight layers, and includes an inner coil member (10B) constituting one layer, three layers, five layers, and seven layers, and an outer coil member (10A) constituting two layers, four layers, six layers, and eight layers. An outer upper right arm bending part (31), an outer upper left arm bending part (32), an outer lower right arm bending part (33), and an outer lower left arm bending part (34) of the outer coil member (10A) are formed, at a position where some portions are not overlaid on each other, when six inner coil members (10B) constituting seven layers are arranged to be overlaid on six outer coil members (10A) constituting eight layers.
US10910898B2
A rotating electric machine having a fraction slot configuration in which the number of slots per pole per phase is not an integer includes: a stator that includes a stator core provided with a plurality of slots, and a stator winding having a plurality of coil sides accommodated in the plurality of slots and a plurality of coil ends connecting the same side end parts of the plurality of coil sides to each other; and a movable element that is supported to be movable with respect to the stator, and includes a movable element core, and a plurality of movable element magnetic poles provided in the movable element core. The stator winding includes a plurality of basic coils in which the magnitude of magnetomotive force generated by the plurality of coil sides forming the one-phase band is uniform in each of the plurality of movable element magnetic poles.
US10910893B2
A rotor for a synchronous reluctance machine having an even number 2 p of poles circumferentially spaced at an angle α, with α=2 π/2 p, the rotor comprising a substantially cylindrical laminate stack having a plurality of magnetically conductive laminations. One or more of the magnetically conductive laminations includes non-magnetic flux barriers which are spaced from each other in the radial direction, one or more of the non-magnetic flux barriers having a first and second bridge transversally positioned in correspondence of their lateral ends and defining a first and a second air-gap with the outer rim of the magnetically conductive lamination, and further including a third and a fourth bridge transversally positioned and respectively defining together with the first and second bridge a first and a second internal space which are filled with an electrically conductive and non-magnetically conductive material.
US10910886B2
A heating system with wireless communication function includes a wireless information transmitting device, a wireless charging transmitting device and a wireless receiving heating device. The wireless information transmitting device includes an external shell, an information transmitting end coil and an information transmitting end magnetic shield. The wireless receiving heating device is disposed on a top surface of the wireless charging transmitting device. The wireless charging transmitting device includes a shell, a transmitting end coil and a transmitting end magnetic shield. The wireless charging transmitting device transmits energy to the wireless receiving heating device by near field induction and the object within the accommodating part of the wireless receiving heating device can be heated. The wireless receiving heating device notifies the wireless charge heating device to increase or decrease energy transmission in a digital communication manner.
US10910885B2
There are included: a switching parameter detecting unit (21) that detects a switching voltage of a switching element (Q1); and an abnormality detecting unit (a first comparing unit (264a) and an abnormality determining unit (265)) that detects an abnormality caused by foreign matter, on the basis of a result of the detection by the switching parameter detecting unit (21).
US10910883B2
In one embodiment, a method includes wirelessly coupling a transmitter to a wireless device; determining a first power transfer value of a signal transmitted from the transmitter to the wireless device with a first transmit impedance; determining a second power transfer value of the signal transmitted from the transmitter to the wireless device with a second transmit impedance; and selecting the first transmit impedance based on received power-level information indicating that the first power transfer value is greater than the second power transfer value.
US10910882B2
Disclosed herein is a receiver device for facilitating wireless energy reception. Accordingly, the receiver device may include a receiver transceiver. Further, the receiver transceiver may be configured for receiving energy wirelessly from at least one transmitter device. Further, the receiver transceiver may be configured for transmitting a registration request to the at least one transmitter device. Further, the registration request may include a unique receiver device identifier. Further, the at least one transmitter device may be configured for analyzing the registration request. Further, the at least one transmitter device may be configured for accessing a distributed block-chain associated with wireless energy transfer based on analyzing. Further, the at least one transmitter device may be configured for authenticating the receiver device based on the accessing. Further, the at least one transmitter device may be configured for transmitting the energy wirelessly to the receiver transceiver based on the authenticating.
US10910875B2
In a backup device, a determination unit determines a first target voltage value of a second power supply unit when a starter switch for starting a vehicle is in an OFF state, so as to be lower than a second target voltage value of the second power supply unit when the starter switch is in an ON state, based on the second target voltage value, a value indicating the charging capability of the charging circuit, and a predetermined time limit. A control unit causes the charging circuit to perform the charging operation upon the starter switch being switched to an ON state, such that the charged voltage of the second power supply unit reaches the second target voltage value, and causes the discharging circuit to perform the discharging operation upon the starter switch being switched to an OFF state, such that the charged voltage reaches the first target voltage value.
US10910860B2
A method, an apparatus and a system for controlling charging of a battery module are provided in the present disclosure. The method for controlling charging of the battery module may include: acquiring an internal pressure value of the battery module; determining a target pressure threshold range to which the acquired internal pressure value of the battery module belongs, based on a plurality of predefined pressure threshold ranges; obtaining a target charge cutoff voltage corresponding to the target pressure threshold range, based on a correspondence relationship between a plurality of predefined charge cutoff voltage and the plurality of predefined pressure threshold ranges; and controlling the battery module to be charged based on the obtained target charge cutoff voltage.
US10910854B2
A tablet computer includes a housing, a display, a processing system, a camera system comprising a camera sensor, and a battery system, the battery system positioned within the housing. The battery system is configured to charge an external device. A charging cable retainer is configured to retain one or more cables against or within the housing. One or more integral cables are provide. The one or more integral cables include a cable comprising a first end fixedly coupled to the battery system, a first connector of a first type configured to mate with a first type of external device connector, a second connector of a second type configured to mate with a second type of external device connector, and a lens configured to form images on the camera sensor. The charging cable retainer includes a cable channel or magnet.
US10910849B2
A charging method includes the following operations: charging an auxiliary power source and at least one charging power source simultaneously, in which a power demand of the auxiliary power source is a first consideration, and a power demand of the at least one charging power source is a second consideration; detecting an auxiliary current value of the auxiliary power source and a total charging current value of the at least one charging power source; and stopping charging the auxiliary power source when a sum of the auxiliary current value and the total charging current value is greater than a current threshold value.
US10910846B2
Systems and methods provide intelligent battery charging and balancing. Energy deficits can be forecasted based on historical data and forecasted energy generation. The deficits can be used to determine charging currents over a period of time, and battery cassettes can be charged according to the charging currents to compensate for the forecasted energy deficit. The states of charge of the battery cassettes can be periodically rebalanced. The battery cassettes can be coupled in series and charged and balanced while providing output to a load.
US10910838B1
An energy management device comprises a first supply/demand information acquisition unit, a second supply/demand information acquisition unit, and a supply/demand management unit configured to determine, based on the first supply/demand information and the second supply/demand information, at least one of (i) an upper limit value of a power amount that the hydrogen generation system can receive from a power grid during a certain period, (ii) a target value of an amount of hydrogen that the hydrogen generation system generates during the certain period, (iii) an upper limit value of a power amount that each of the one or plurality of tri-generation systems can transmit to the power grid during the certain period, and (iv) a target value of a power amount that each of the one or plurality of tri-generation systems generates during the certain period.
US10910835B1
Adaptive protection methods and systems for protecting agains) extreme fault currents in a power system are provided. Communication capabilities and protocols defined in IEC 61850 can be used to provide smart cascading switching actions for removing the fault from the power system. A supervisory protection algorithm can be used, and the protection can be activated if the fault current is higher than a breaking capacity of the circuit breakers of the power system.
US10910827B2
A solid state power controller, SSPC, having an input to receive supply current and an output for providing output current to a load in response to connection to the power supply, the solid state power controller further comprising at least one solid state switch and a controller to limit the power dissipated in the solid state power switch based on a measured voltage across the solid state switch and a predetermined power dissipation threshold for the SSPC to adjust the output current or voltage control signal of the solid state switch such that the actual power dissipation of the SSPC does not exceed the threshold.
US10910825B2
A system for an electrical power distribution network includes an electrical apparatus configured to monitor or control one or more aspects of the electrical power distribution network, the electrical apparatus including a contact switch configured to open and close. The system also includes an input apparatus. The input apparatus includes an impedance module; and an input interface electrically connected to the impedance module and to the contact switch of the electrical apparatus. The input interface is configured to have one of a plurality of input impedances, the plurality of input impedances include at least a first input impedance and a second input impedance that is lower than the first input impedance, and the input interface has the second input impedance when the contact switch of the electrical apparatus is open. The input apparatus may include a plurality of leakage current detection modules.
US10910822B2
A system includes a first transistor having a first control input and first and second current terminals. The first current terminal couples to an input voltage node. A second transistor has a second control input and third and fourth current terminals. The third current terminal couples to the second current terminal at a first node. The fourth current terminal couples to an output voltage node. A drive circuit is configured to charge a capacitor maintain the first transistor in an off state responsive to a negative voltage on the input voltage node, and, responsive to a negative voltage on the input voltage node, to cause the charge from the capacitor to be used to turn off the first transistor. The system provides a voltage to a load coupled to the output voltage node.
US10910814B2
A receptacle including an electronic processor configured to receive information from an external load and determine, from the information, an operation profile of the external load. The electronic processor analyzes a present operation of the external load and discontinues power to the external load when a present operation of the external load differs from the operational profile.
US10910810B2
A gel sealing device includes a gel sealing block (5) which provides a sealing section (22) through which the elongate parts (13, 14) extend. The gel sealing block (5) includes an upper flange (11) and a lower flange (12) with a support section (11a, 12a, 12b) disposed therebetween. The upper and lower flanges (11, 12) sandwiches, in direction of extension of the elongate parts (13, 14), a gel inner ring (7) supported by said support section (2) and a gel outer ring (6, 10a) covering the gel inner ring (7) in a radial direction extending transverse to said extension direction. The gel inner ring (7) and the gel outer ring (6, 10a) are made of a gel sealing material.
US10910804B2
A cable management device includes a first cable management arm, a second cable management arm and an auxiliary member. The second cable management arm is movable relative to the first cable management arm. The auxiliary member is extendable and retractable relative to one of the first cable management arm and the second cable management arm. When the auxiliary member is moved relative to the one of the first cable management arm and the second cable management arm, a length direction of the auxiliary member is parallel to a length direction of the one of the first cable management arm and the second cable management arm, and the auxiliary member is movable along the length direction of the one of the first cable management arm and the second cable management arm.
US10910793B2
A laser or light emitter for operation at a cryogenic temperature includes a single quantum well layer, an n-type barrier layer directly on a first surface of the single quantum well layer, and a p-type barrier layer directly on a second surface of the single quantum well layer opposite the first surface of the single quantum well layer. The single quantum well layer is between the p-type barrier layer and the n-type barrier layer and the compositions of the n-type barrier layer and the p-type barrier layer are graded.
US10910792B2
Hybrid silicon lasers are provided including a bulk silicon substrate, a localized insulating layer that extends on at least a portion of the bulk silicon substrate, an optical waveguide structure on an upper surface of the localized insulating layer. The optical waveguide structure includes an optical waveguide including a silicon layer. A lasing structure is provided on the optical waveguide structure.
US10910790B2
Embodiments pertain to a semiconductor device package, a method of manufacturing the semiconductor device package, and an autofocusing apparatus including the semiconductor device package. The semiconductor device package according to an embodiment may include: a package body; a diffusion unit; and a vertical cavity surface emitting laser (VCSEL) semiconductor device disposed on a support and under the diffusion unit. According to the embodiment, the package body may include the support, a first sidewall protruding to a first thickness from an edge region of an upper surface of the support and having a first upper surface of a first width, and a second sidewall protruding to a second thickness from the first upper surface of the first side wall and having a second upper surface of a second width, wherein the support, the first sidewall, and the second sidewall may be integrally formed with the same material. The diffusion unit may be disposed on the first upper surface of the first sidewall and may be disposed to be surrounded by the second sidewall.
US10910786B2
The disclosure describes aspects of laser cavity optical alignment, and more particularly, in situ alignment of optical devices in an optical system for replacement or upgrade. In one aspect, a method for optical alignment in an optical system is described that includes providing, via a positioning system, an optical beam to measure surface features and position of a first device under test (DUT), removing the first DUT from the optical system, placing a second DUT in the optical system at substantially the same position from which the first DUT was removed, providing, via the positioning system, an optical beam to measure surface features and position of the second DUT, aligning the second DUT based on the measurements made of the first DUT and the second DUT, and verifying operation of the second DUT in the optical system. The DUT can be an optical device such as an output optical coupler.
US10910779B2
A connector including a first connector and a second connector configured to face each to fit together. The first connector includes a first internal terminal including terminals along a longitudinal direction, a first insulating member supporting the first internal terminal, and first external terminals at two ends of the first internal terminal in the longitudinal direction. The second connector includes a second internal terminal including terminals along a longitudinal direction and that engages with the first internal terminal, a second insulating member supporting the second internal terminal, and second external terminals at two ends of the second internal terminal in the longitudinal direction. The first connector includes projecting portions that project further toward the second connector than the first internal terminal does in a fitting direction. The second connector includes recesses that accommodate the projecting portions and guiding portions, each being in a vicinity of one of the recesses.
US10910775B2
A drive element for an electrical connector comprises a gear wheel and an overload coupler. The overload coupler is between the gear wheel and a hub.
US10910765B2
A lever-type connector has a lever that rotates about a shaft on a first housing between a retracted position and a connection start position. The first housing and a second housing are connected by rotation of the lever from the connection start position. A detector is movable between a standby position and a detection position with respect to the lever. The lever includes a lock on an end separated from the shaft. The second housing includes a full locking portion to engage the lock when the housings are connected. The detector locks the lock at the standby position and becomes movable to the detection position when the full locking portion engages the lock. The first housing includes a housing-side lock, and the lever includes a lever-side lock that locks the housing-side lock at the retracted position. The lever-side lock is at a position different from the lock of the lever.
US10910763B2
A cable-connector assembly includes: a cable including signal-carrying members, the signal-carrying members being circumferentially surrounded by a conduit; a connector configured to mate with a mating connector, the signal carrying members being connected with ports on the connector; and a generally cylindrical housing that circumferentially surrounds the signal-carrying members, the housing including a narrow neck that fits within an end of the conduit and a wide main portion that engages the connector.
US10910759B2
A connector includes a plurality of contacts, a holding member and a shell. The holding member has a main portion and a tongue portion. The main portion includes three or more positioned portions. The shell is formed with a hole and three or more positioning protrusions. The hole has a closed periphery on a surface of the shell. The hole pierces the shell in a first direction perpendicular to a mating direction. The positioning protrusions occupy zones, respectively, in the mating direction. The zones overlap with each other in the mating direction. The positioning protrusions include a first positioning protrusion and two second positioning protrusions. The first positioning protrusion forms a part of the closed periphery of the hole. The first positioning protrusion faces the hole. When the shell is viewed alone, at least one of the second positioning protrusions is visible through the hole.
US10910753B2
It is aimed to realize miniaturization. A connector includes a terminal unit (50) having a terminal holding member (51) and configured to be displaced between a partial locking position and a full locking position integrally with a retainer (30), a terminal fitting (58) mounted in the terminal holding member (51) such that a draw-out direction of a wire (61) is a direction intersecting a displacing direction of the retainer (30), a stopper (25) formed in the housing (10) and facing in a direction opposite to the draw-out direction of the wire (61), and a butting portion (54) formed on the terminal holding member (51), the butting portion being not locked to the stopper (25) with the retainer (30) held at the partial locking position and being lockable to the stopper (25) by a displacement of the retainer (30) to the full locking position.
US10910744B2
A vehicular camera includes a front housing portion that accommodates a lens and an imager, a circuit board disposed at the front housing portion, a rear housing portion and a coaxial connecting element at the rear housing portion. The coaxial connecting element includes a first coaxial connector portion and a second coaxial connector portion. The first coaxial connector portion extends outward from the rear housing portion and the second coaxial connector portion extends inward from the rear housing portion. The circuit board has a coaxial connector established thereat. When the rear housing portion is mated with the front housing portion, the second coaxial connector portion electrically connects to the coaxial connector to electrically connect the coaxial connecting element with circuitry at the circuit board. The first coaxial connector portion is configured to connect to a coaxial cable of a vehicle when the vehicular camera is disposed at the vehicle.
US10910731B2
A flat panel antenna is provided. The flat panel antenna may include a plurality of flat panel arrays (FPAs) that are arranged adjacent one another. Ones of the plurality of FPAs are configured to radiate in a plurality of different respective frequency bands and/or at different respective polarizations. The flat panel antenna includes an enclosure that defines an internal cavity that includes the plurality of FPAs.
US10910724B2
Disclosed are multi-band trace antennas and circuit boards including a multi-band trace antenna for the transmission and/or reception of information in a wireless communication system. The circuit board is configurable to include a multi-band trace antenna. Additionally, the circuit board can comprise a feed point adjacent an edge of the circuit board, the feed point being connected to a pair of closely coupled traces of unequal length, a first of the traces extending away from the feed point along the edge of the circuit board, and a second of the traces extending away from the feed point inboard of the first antenna trace, the circuit board comprises a ground plane coplanar with the traces, an edge of the ground plane extending alongside and closely coupled with the second of the traces to cause an area of the ground place adjacent the edge to radiate at a selected lower operational frequency of the antenna, wherein an edge of a longer of the pair of closely coupled traces is indented to vary a width of the trace at a plurality of points along its length and to increase radiation of the shorter of the pair of closely coupled traces at a selected higher operational frequency of the antenna.
US10910720B2
An antenna includes a dielectric, first to fourth antenna electrodes, and at least one probe electrode. The dielectric has first to fifth planes stacked parallel to each other in a stacking direction. The first to the fourth antenna electrodes each have an annular shape. The first antenna electrode is disposed on the first plane. The second antenna electrode is different in size from the first antenna electrode and disposed on the second plane. The third antenna electrode is disposed on the third plane. The fourth antenna electrode is different in size from the third antenna electrode and disposed on the fourth plane. The probe electrode is disposed on the fifth plane and overlaps one or both of the first and third antenna electrodes and one or both of the second and fourth antenna electrodes when seen in plan view along the stacking direction.
US10910717B2
An antenna device including a first rod-shaped core having a flange portion and a second rod-shaped core having a flange portion, which are arranged in series and including a first coil and a second coil, wherein the end surface of the first rod-shaped core and the end surface of the second rod-shaped core are spaced.
US10910714B2
A signal processing circuit reduces die size and power consumption for each antenna element. The signal processing circuit includes a first set of ports, a third port, a first path, a second path and a first transistor. The first path is between a first port of the first set of ports and the third port. The second path is between a second port of the first set of ports and the third port. The first transistor is coupled between the first path and the second path. The first transistor is configured to receive a control signal to control the first transistor to adjust an impedance between the first path and the second path.
US10910710B2
Systems and methods are provided for distortion redirection in phased arrays. In an electronic device configured for transmission and reception of signals and having a two-dimensional phased array, effects of distortion, corresponding to at least one processing function applied during communication of signals, on the communication of signals may be assessed, and based on the effects of distortion, one or more adjustments for mitigating the effects of distortion may be configured and applied during processing of signals. Assessing the effects of distortion may include determining one or more characteristics associated with the communication of the signals, where the one or more characteristics relate and/or are subject to the effects of the distortion, and assessing the effects of distortion based on the one or more characteristics.
US10910704B2
A system for manufacturing an antenna includes a first stamping station, a pressure sensitive adhesive (PSA) alignment station, a bonding station, a second stamping station, and a ferrite shield station. The first stamping station receives a sheet of metallic material and stamps the sheet to form an antenna including traces, contacts, a carrier connected to the traces, and a tie-bar connected between the traces. The PSA alignment station receives the stamped antenna and aligns a PSA area of a pad with the traces, the PSA area being substantially the same shape as the traces. The bonding station bonds the PSA area to the traces after it has been aligned with the traces. The second stamping station performs a second stamping of the antenna and the PSA area to remove the carrier and the tie-bar. The ferrite shield station bonds a ferrite shield to the antenna stamped for a second time.
US10910699B2
A triple-band antenna array for cellular base stations operates at a first frequency band and at a second frequency band within a first frequency range, and also at a third frequency band within a second frequency range. The triple-band antenna array comprises a first set of radiating elements operating at the first frequency band, a second set of radiating elements operating at the second frequency band, a third set of radiating elements operating at both the third and the first frequency bands, and a fourth set of radiating elements operating at both the third and the second frequency bands. The radiating elements are arranged such that at least some of the radiating elements of the first and third sets are interlaced, and at least some of the radiating elements of the second and fourth sets are interlaced.
US10910695B2
An on-chip antenna includes an integrated circuit chip, a reflective conductor, at least one first coupler, at least one patch antenna element, a connection, and at least one second coupler. The integrated circuit chip includes a semiconductor, has an active surface and a back surface opposed to each other, and has a semiconductor circuit. The reflective conductor is disposed above the back surface. The at least one first coupler is disposed between the back surface and the reflective conductor. The at least one patch antenna element is disposed above the reflective conductor. The connection couples the at least one patch antenna element and the at least one first coupler. The at least one second coupler is provided on the active surface to be electrically conductive to the semiconductor circuit, and is opposed to the at least one first coupler and in non-contact with the at least one first coupler.
US10910686B2
An electrochemical cell includes a permeable fuel electrode configured to support a metal fuel thereon, and an oxidant reduction electrode spaced from the fuel electrode. An ionically conductive medium is provided for conducting ions between the fuel and oxidant reduction electrodes, to support electrochemical reactions at the fuel and oxidant reduction electrodes. A charging electrode is also included, selected from the group consisting of (a) the oxidant reduction electrode, (b) a separate charging electrode spaced from the fuel and oxidant reduction electrodes, and (c) a portion of the permeable fuel electrode. The charging electrode is configured to evolve gaseous oxygen bubbles that generate a flow of the ionically conductive medium. One or more flow diverters are also provided in the electrochemical cell, and configured to direct the flow of the ionically conductive medium at least partially through the permeable fuel electrode.
US10910685B2
Vehicle having a high-voltage battery which has a housing, wherein the housing has a housing floor which is essentially parallel to an underlying surface on which the vehicle is standing or travelling, a housing cover which is arranged spaced apart from the housing floor, housing walls via which the housing floor is connected to the housing cover. The housing has at least one housing structure plate which has a plane of maximum size which is perpendicular with respect to the housing floor and with respect to the housing cover, and an underside which faces the housing floor or is connected thereto, and an upper side which faces the housing cover or is connected thereto. In an interior space of the housing structure plate at least two parallel cooling ducts are provided, through which coolant or a cooling agent flows, and on a first side and a second side, lying opposite the first side, of the housing structure plate at least one electrical storage cell is respectively arranged, in particular a multiplicity of electrical storage cells are respectively arranged, wherein the storage cells each have a positive and a negative connecting pole. At least one connecting pole or both connecting poles of the storage cells is/are connected to the first and/or second side of the housing structure plate in a thermally conductive and electrically insulated fashion.
US10910680B2
A battery thermal management system according to an exemplary aspect of the present disclosure includes, among other things, a battery pack, a coolant subsystem configured to cool the battery pack, and a thermoelectric device disposed within the coolant subsystem and selectively activated to augment cooling of the battery pack.
US10910668B2
A battery system 5 is provided with an all-solid-state battery 10, a voltage detection device that detects voltage of the all-solid-state battery, a current detection device 66 that detects current flowing from the all-solid-state battery, and a control device 50 that controls the all-solid-state battery. A negative electrode active material layer is composed of lithium metal. The control device calculates the amount of change in charging rate as a first estimated value, based on an integrated value obtained by integrating detected current over a prescribed calculation period, calculates the amount of change in charging rate as a second estimated value, based on voltage detected during the calculation period as a second estimated value, and judges that an abnormality has occurred in the all-solid-state battery when the difference between the first estimated value and the second estimated value is equal to or greater than a predetermined reference value.
US10910665B2
Disclosed herein are provided a lithium secondary battery capable of improving an output characteristic, a life characteristic, and stability of electrode adhesion by using a binder containing dopamine-polymerized heparin in a anode containing silicon. In accordance with an aspect of the present disclosure, a lithium secondary battery includes: an cathode; a anode; a separation film disposed between the cathode and the anode; and an electrolyte, wherein the anode comprises an electrode active material comprising a silicon-based material and graphite, a binder and a conductive material, and the binder comprises any one of heparin and lithium polyacrylate (LiPAA).
US10910644B2
A nickel-hydrogen battery includes a plurality of electrodes each including a current collector made of a metal, and disposed in a manner stacked in a first direction; a separator disposed between adjacent electrodes of the plurality of electrodes; a plurality of resin members disposed on peripheral portions of the plurality of electrodes to ensure a clearance between the adjacent electrodes; and a surface treatment layer covering one surface of the current collector at least in the peripheral portion of the plurality of electrode. The surface treatment layer includes a plurality of protrusions from the one surface. Widest parts of the protrusions are located above base ends thereof, and parts of the resin members are interposed between adjacent protrusions, across a range from tip ends to the base ends thereof.
US10910637B2
Provided are a positive electrode and a lithium secondary battery which have high energy capacity and include a nickel-containing positive electrode active material, and an additive including metal particles and lithium oxide.
US10910627B2
The disclosure is related to a battery formation system and probe supporting structure thereof. The battery formation system includes a base, a holder, a probe supporting structure and at least one probe. The base is adaptive to bear at least one battery, and the holder is located on one side of the base. The probe supporting structure is disposed on the holder. The probe supporting structure has an air flow passage and at least one air discharge channel connected to each other, and an extension direction of the air flow passage intersects an extension direction of the at least one air discharge channel. The at least one probe is disposed on the probe supporting structure, and a probing end of the at least one probe and an air outlet of the at least one air discharge channel are located at a same side of the probe supporting structure.
US10910625B2
Battery parts having retaining and sealing features and associated assemblies and methods are disclosed herein. In one embodiment, a battery part includes a base portion that is configured to be embedded in battery container material of a corresponding battery container. The battery part and base portion include several torque resisting features and gripping features that resist torsional or twist loads that are applied to the battery part after it has been joined to the battery container. For example, the base portion can include several internal and external torque resisting features and gripping features that are configured to resist twisting or loosening of the battery part with reference to the battery container material, as well as prevent or inhibit fluid leakage from the battery container.
US10910622B2
A connection member and a rechargeable battery are provided. The connection member includes a guide plate, two first connection plates and a second connection plate; the two first connection plates are respectively connected to two sides of the guide plate in a width direction and are arranged bendably with respect to the guide plate; the second connection plate is connected to an upper end of the guide plate in a height direction Z, and the top ends of the two first connection plates are at different heights. In some examples, overcurrent capability of the connection member and rapid charging capability and safety performance of the rechargeable battery can be improved.
US10910614B2
This disclosure details electrified vehicles that are equipped with secondary battery packs for increasing the electric range of the vehicles. An exemplary electrified vehicle includes a cargo space, such as a truck bed, and a secondary battery pack positioned within the cargo space. The secondary battery pack is adapted to selectively supply power for propelling one or more vehicle drive wheels. In some embodiments, the secondary battery pack is shaped like, and therefore disguised as, a toolbox.
US10910598B2
A lighting apparatus using an organic light emitting diode that has a first area and a second area, the lighting apparatus comprises a substrate; a barrier layer disposed on the substrate; an auxiliary line disposed in the first area on the substrate; a first electrode disposed on an entire surface of the substrate; an organic layer disposed on the first electrode; and a second electrode disposed on the organic layer, wherein the barrier layer includes a first inorganic barrier layer, an organic barrier pattern disposed in the second area, and a second inorganic barrier layer.
US10910597B2
An object of one embodiment of the present invention is to provide a more convenient highly reliable light-emitting device which can be used for a variety of applications. Another object of one embodiment of the present invention is to manufacture, without complicating the process, a highly reliable light-emitting device having a shape suitable for its intended purpose. In a manufacturing process of a light-emitting device, a light-emitting panel is manufactured which is at least partly curved by processing the shape to be molded after the manufacture of an electrode layer and/or an element layer, and a protective film covering a surface of the light-emitting panel which is at least partly curved is formed, so that a light-emitting device using the light-emitting panel has a more useful function and higher reliability.
US10910588B2
A display device includes a substrate including an upper surface, a lower surface, and side surfaces; a display element layer on the upper surface overlapping the display area; an encapsulation layer on the upper surface, the encapsulation layer including a main part that overlaps the display element layer and a protruding part that protrudes along a first direction from the main part and overlaps the bezel area; an input sensor on the main part; a first circuit board facing the main part, overlapping the bezel area, and on the upper surface; and a second circuit board on the protruding part, wherein each of the first circuit board and the second circuit board is adjacent to a first side surface among the side surfaces, and in the first direction, the protruding part is more adjacent to the first side surface than the main part.
US10910586B2
A lighting apparatus including organic light-emitting diodes comprises an anode disposed in an emission area of a substrate; first and second pad electrodes disposed on an outer side of the emission area of the substrate; a short-circuit reduction pattern surrounding an emission zone of each of pixels and formed by removing a part of the anode; a passivation layer comprising the short-circuit reduction pattern and disposed on the anode; an organic layer and a cathode disposed on the passivation layer in the emission area of the substrate; and a metal film disposed in the emission area of the substrate, wherein the short-circuit reduction pattern has a gradually-reducing resistance with an increased distance between the pixels and the first and second pad electrodes.
US10910574B2
A display panel, terminal, and method are provided for display control in the technical field of display. The display panel may include: an image display panel; an optical sensor array in the image display panel. The optical sensor array may include a plurality of optical sensors arranged in an array. The display further includes a grating panel disposed above the optical sensor array. The grating panel includes an optical shading area that is not overlapped with an optical sensing area of the optical sensors.
US10910572B2
A flexible display device including: a display substrate having a display area and a peripheral area surrounding the display area; a plurality of pixels formed in the display area; a passivation layer covering the pixels from the top to protect the pixels; a polarization film layer provided at the top of the passivation layer and of which an edge is extended outside an edge of the passivation layer; and a film wiring made of a flexible material of which one end is connected to the peripheral area.
US10910561B1
Providing for two-terminal memory that mitigates diffusion of external material therein is described herein. In some embodiments, a two-terminal memory cell can comprise an electrode layer. The electrode layer can be at least in part permeable to ionically or chemically reactive material, such as oxygen or the like. The two-terminal memory can further comprise a diffusion mitigation material disposed between the electrode layer and external material. This diffusion mitigation material can be selected to mitigate or prevent diffusion of the undesired element(s) or compound(s), to mitigate or avoid exposure of such element(s) or compound(s) to the electrode layer. Accordingly, degradation of the two-terminal memory as a result of contact with the undesired element(s) or compound(s) can be mitigated by various disclosed embodiments.
US10910554B2
A spin-current magnetization rotational element includes a spin orbit torque wiring extending in a first direction and a first ferromagnetic layer disposed in a second direction intersecting the first direction of the spin orbit torque wiring, the spin orbit torque wiring having a first surface positioned on the side where the first ferromagnetic layer is disposed, and a second surface opposite to the first surface, and the spin orbit torque wiring has a second region on the first surface outside a first region in which the first ferromagnetic layer is disposed, the second region being recessed from the first region to the second surface side.
US10910542B2
A laminated thermoelectric conversion element is a laminated thermoelectric conversion element that has: a first end surface and a second end surface opposed to each other; a heat absorption surface; and a heat release surface, where p-type thermoelectric conversion material layers and n-type thermoelectric conversion material layers are electrically connected and at the same time, laminated alternately in a meander form with insulating layers partially interposed there between, in an intermediate part, the p-type thermoelectric conversion material layers are laminated which have a p-type basic thickness, whereas the n-type thermoelectric conversion material layers are laminated which have an n-type basic thickness, and the thickness of the p-type thermoelectric conversion material layer or n-type thermoelectric conversion material layer outside the insulating layer located closest to any of the first end surface and second end surface is larger as compared with the basic thickness of the thermoelectric conversion material layer with the same type of conductivity.
US10910541B2
A thermoelectric element according to one embodiment of the present invention comprises: a first substrate; a plurality of P-type thermoelectric legs and a plurality of N-type thermoelectric legs that are alternately arranged on the first substrate; a second substrate disposed on the plurality of P- and N-type thermoelectric legs; and a plurality of electrodes that connect the plurality of P- and N-type thermoelectric legs in series, wherein the plurality of electrodes include a plurality of first electrodes disposed between the first substrate and the plurality of P- and N-type thermoelectric legs, and a plurality of second electrodes disposed between the second substrate and the plurality of P- and N-type thermoelectric legs, and grains constituting at least one of the plurality of first and second electrodes grow in the direction from the first substrate to the second substrate.
US10910538B2
An optoelectronic semiconductor component and a method for producing an optoelectronic semiconductor component are disclosed. In an embodiment an optoelectronic semiconductor component includes a plurality of active regions configured to emit electromagnetic radiation, wherein the active regions are arranged spaced apart from each other, wherein the active regions have a main extension direction, wherein each active region has a core region, an active layer covering the core region at least in directions transverse to the main extension direction, wherein each active region has a cover layer covering the active layer at least in directions transverse to the main extension direction, wherein each active region has a current spreading layer at least partly covering sidewalls of each respective active region, and wherein a metal layer directly adjoins parts of the active regions and parts of the current spreading layers.
US10910536B2
The light emitting element includes: first and second light emitting cells each including an n-side semiconductor layer, an active layer and a p-side semiconductor layer; a first insulating film covering the first and second light emitting cells, and provided with first p-side and first n-side openings; a wiring electrode connected to the first light emitting cell at the first n-side opening, and connected to the second light emitting cell at the first p-side opening; a first electrode connected to the first light emitting cell; a second electrode connected to the second light emitting cell; a second insulating film provided with a second p-side opening formed above the first electrode, a second n-side opening formed above the second electrode, and a third opening formed above the wiring electrode; a first external connection portion connected to the first electrode; and a second external connection portion connected to the second electrode.
US10910535B2
A method for making light emitting device LED arrays includes the steps of providing a plurality of LEDs having a desired configuration (e.g., VLED, FCLED, PLED); attaching the LEDs to a carrier substrate and to a temporary substrate; forming one or more metal layers and one or more insulator layers configured to electrically connect the LEDs to form a desired circuitry; and separating the LEDs along with the layered metal layers and insulator layers that form the desired circuitry from the carrier substrate and the temporary substrate.
US10910534B2
According to one embodiment, the light guide plate has a first major surface, a second major surface, a side surface, and a recess. The recess is provided in the second major surface. The fluorescent layer is provided in the recess. The light-emitting element is bonded to the fluorescent layer and includes an electrode on a surface of the light-emitting element on a side opposite to a surface of the light-emitting element bonded to the fluorescent layer. The module side surface includes at least a portion of the side surface of the light guide plate. The first interconnect is provided along the second major surface and connected to the electrode of the light-emitting element. The second interconnect is provided on the module side surface and connected to the first interconnect.
US10910532B2
A semiconductor device package is provided, which includes a carrier, an emitter and a first transparent encapsulant. The carrier has a first surface. The emitter is disposed on the first surface. The first transparent encapsulant encapsulates the emitter. The first transparent encapsulant includes a body and a lens portion. The body has a first planar surface. The lens portion is disposed on the body and has a first planar surface. The first planar surface of the lens portion is substantially coplanar with the first planar surface of the body.
US10910531B2
An optoelectronic component and a method for producing an optoelectronic component are disclosed. In an embodiment an optoelectronic component includes an optical element including silicone as a polymer material, the silicone having repeating units of cyclic siloxane and of linear siloxane which are arranged in alternation, wherein the optoelectronic component is configured to emit radiation.
US10910529B2
In a method according to embodiments of the invention, for a predetermined amount of light produced by a light emitting diode and converted by a phosphor layer comprising a host material and a dopant, and for a predetermined maximum reduction in efficiency of the phosphor at increasing excitation density, a maximum dopant concentration of the phosphor layer is selected.
US10910528B2
This disclosure discloses an LED assembly. The LED assembly includes a transparent mount with a top surface and a bottom surface opposite to the top surface, an LED chip arranged on the top surface, an electrode plate, a first phosphor layer having a first phosphor, and a second phosphor layer having a second phosphor, wherein the transparent mount and the electrode plate substantially have a same width. The electrode plate is arranged on an edge of the top surface and electrically connected to the LED chip.
US10910527B2
An optoelectronic component is disclosed. In an embodiment, an optoelectronic component includes a semiconductor chip configured to emit primary radiation having a peak wavelength between 420 nm inclusive and 480 nm inclusive and a conversion element including a first converter material configured to partially convert the primary radiation into secondary radiation in a green range of the electromagnetic spectrum and a second converter material configured to partially convert the primary radiation into a secondary radiation in a red region of the electromagnetic spectrum, wherein the second converter material including a first red phosphor of the formula (K,Na)2(Si,Ti)F6:Mn4+ and a second red phosphor of the formula(M′)2-x′Eux′Si2Al2N6 where M′=Sr, Ca, Ba, and/or Mg and 0.001≤x′≤0.2, and wherein the optoelectronic device is configured to emit white total radiation.
US10910519B2
An embodiment discloses a semiconductor device including a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer; a first electrode electrically connected with the first conductive semiconductor layer; and a second electrode electrically connected with the second conductive semiconductor layer, and a semiconductor device package including the same. The second conductive semiconductor layer includes a first surface on which the second electrode is disposed. The second conductive semiconductor layer has a ratio of a second shortest distance W2, which is a distance from the first surface to a second point, to a first shortest distance W1, which is a distance from the first surface to a first point, (W2:W1) ranging from 1:1.25 to 1:100. The first point is a point at which the second conductive semiconductor layer has the same aluminum composition as a well layer of the active layer closest to the second conductive semiconductor layer. The second point is a point at which the second conductive semiconductor layer has the same dopant composition as the aluminum composition.
US10910512B2
The present invention relates to a nano-scale light-emitting diode (LED) element for a horizontal array assembly, a manufacturing method thereof, and a horizontal array assembly including the same, and more particularly, to a nano-scale LED element for a horizontal array assembly that can significantly increase the number of nano-scale LED elements connected to an electrode line, facilitate an arrangement of the elements, and implement a horizontal array assembly having a very good electric connection between an electrode and an element and a significant high quantity of light when a horizontal array assembly having the nano-scale LED elements laid in a length direction thereof and connected to the electrode line is manufactured, a manufacturing method thereof, and a horizontal array assembly including the same.
US10910508B1
A method is provided for fabricating a backside-illuminated photodetector in which a device wafer is joined to a readout wafer in an IC hybridization step. Before the IC hybridization step, the device layer is defined in the device wafer, and an LPCVD layer is formed over the device layer. The LPCVD layer may be a passivation layer, an antireflection coating, or both. The side of the device wafer having the LPCVD layer is bonded to a handle wafer, the IC is hybridized by mating the device wafer to the readout wafer, and the handle wafer is then removed, exposing the LPCVD layer. Because the LPCVD layer is formed before the active devices are fabricated, it can be made by high-temperature techniques for deposition and processing. Accordingly, a layer of high quality can be fabricated without any hazard to the active devices.
US10910504B2
[Object] To propose a solid-state imaging element, an imaging device, and a method for manufacturing a solid-state imaging element that are capable of providing a pixel with polarization sensitivity while suppressing the reduction in sensitivity to non-polarized incident light. [Solution] A solid-state imaging element according to the present disclosure includes: a light receiving element included in a plurality of pixels; and a groove section provided on surfaces of at least some of the pixels in the light receiving element and extended along a prescribed direction. Two or more directions including at least mutually orthogonal two directions exist as a direction in which the groove section is extended.
US10910496B2
A semiconductor device includes a fin-like structure extending along a first axis; a first source/drain feature disposed at a first end portion of the fin-like structure; and a constraint layer disposed at a first side of the first end portion of the fin-like structure, wherein the first source/drain feature comprises a first portion, disposed at the first side, the first portion comprising a shorter extended width along a second axis, and a second portion, disposed at a second side that is opposite to the first side, the second portion comprising a longer extended width along the second axis.
US10910489B2
A semiconductor device according to an embodiment includes: a substrate; a first nitride semiconductor layer that is provided above the substrate, has a first lattice period in a first direction parallel to a substrate plane, and includes nitrogen and aluminum; a second nitride semiconductor layer that is provided between the substrate and the first nitride semiconductor layer and includes nitrogen and aluminum and of which at least a portion has a second lattice period that is three times the first lattice period in the first direction parallel to the substrate plane; a third nitride semiconductor layer provided above the first nitride semiconductor layer; a fourth nitride semiconductor layer that is provided on the third nitride semiconductor layer and has a larger bandgap than the third nitride semiconductor layer; at least one main electrode provided on the fourth nitride semiconductor layer; and a control electrode provided above the third nitride semiconductor layer, the control electrode being configured to control a current of the semiconductor device.
US10910485B2
In a surface layer of a rear surface of the semiconductor substrate, an n+-type cathode region and a p-type cathode region are each selectively provided. The n+-type cathode region and the p-type cathode region constitute a cathode layer and are adjacent to each other along a direction parallel to the rear surface of the semiconductor substrate. The n+-type cathode region and the p-type cathode region are in contact with a cathode electrode. In an n−-type drift layer, plural n-type FS layers are provided at differing depths deeper from the rear surface of the semiconductor substrate than is the cathode layer. With such configuration, in a diode, a tradeoff relationship of forward voltage reduction and reverse recovery loss reduction may be improved and soft recovery may be realized.
US10910484B2
On a single-crystal semiconductor substrate with an upper surface including a first direction in which an inverted mesa step extends and a second direction in which a forward mesa step extends in response to anisotropic etching in which an etching rate depends on crystal plane orientation, a bipolar transistor including a collector layer, a base layer, and an emitter layer that are epitaxially grown, and a base wire connected to the base layer are arranged. A step is provided at an edge of the base layer, and the base wire is extended from inside to outside of the base layer in a direction intersecting the first direction in a plan view. An intersection of the edge of the base layer and the base wire has a disconnection prevention structure that makes it difficult for step-caused disconnection of the base wire to occur.
US10910483B2
A method and structure for forming a fin bottom diode includes providing a substrate having a plurality of fins extending therefrom. Each of the plurality of fins includes a substrate portion and an epitaxial layer portion over the substrate portion. A first dopant layer is formed on sidewalls of a first region of the substrate portion of each of the plurality of fins. After forming the first dopant layer, a first annealing process is performed to form a first diode region within the first region of the substrate portion. A second dopant layer is formed on sidewalls of a second region of the substrate portion of each of the plurality of fins. After forming the second dopant layer, a second annealing process is performed to form a second diode region within the second region of the substrate portion of each of the plurality of fins.
US10910479B2
A semiconductor device includes a substrate; a fin structure formed on a substrate; and a gate feature formed over the fin structure, the gate feature comprising a gate dielectric layer, wherein the gate dielectric layer traverses the fin structure to overlay a central portion of the fin structure and opposite side portions of the fin structure that are located in respective undercuts formed in respective portions of a dielectric layer located adjacent to opposite sidewalls of the gate feature, wherein the undercuts extend beyond respective sidewalls of the gate feature and away from the central portion of the fin structure.
US10910475B2
A method of manufacturing a silicon wafer includes extracting an n-type silicon ingot over an extraction time period from a silicon melt comprising n-type dopants, adding p-type dopants to the silicon melt over at least part of the extraction time period, so as to compensate an n-type doping in the n-type silicon ingot by 20% to 80%, and slicing the silicon ingot.
US10910474B2
A method for manufacturing a group III nitride semiconductor substrate includes a preparation step S10 for preparing a group III nitride semiconductor substrate having a sapphire substrate having a semipolar plane as a main surface, and a group III nitride semiconductor layer positioned over the main surface, in which a <0002> direction of the sapphire substrate and a <10-10> direction of the group III nitride semiconductor layer do not intersect at right angles in a plan view in a direction perpendicular to the main surface, and a growth step S20 for epitaxially growing a group III nitride semiconductor over the group III nitride semiconductor layer.
US10910469B2
A semiconductor device includes a substrate and a conducting structure. The substrate has a first conductivity type and includes a first isolation region, a first implant region, and a second implant region. The first isolation region is disposed along the circumference of the substrate. The first implant region has the first conductivity type, and the second implant region has a second conductivity type that is the opposite of the first conductivity type. The conducting structure is disposed on the substrate, and at least a portion of the conducting structure is located on the first isolation region.
US10910466B2
A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.
US10910462B2
A display substrate, a method for manufacturing the same and a display device are provided. The display substrate includes a base substrate, first electrodes above the base substrate, and a light emitting layer disposed at a side of the first electrodes distal from the base substrate, the display substrate further includes signal lines extending in a first direction and fuse wires extending in a second direction, each fuse wire has a fusing point higher than that of the light emitting layer, the fuse wires are located at a side of the light emitting layer proximal to the base substrate and in contact with the light emitting layer, each fuse wire is electrically coupled to at least two signal lines, and an orthographic projection of at least one first electrode on the base substrate is located between orthographic projections of the at least two signal lines on the base substrate.
US10910461B2
A display panel includes a substrate having a first area and a second area, a non-display area surrounding the first area and the second area, and a display area surrounding the non-display area, a plurality of display elements arranged in the display area, and a plurality of signal lines electrically connected to the plurality of display elements, wherein the plurality of signal lines includes a first signal line and a second signal line neighboring each other and extending in a first direction, wherein the first signal line bypasses in the non-display area along a first side of the first area, and the second signal line bypasses in the non-display area along a second side of the first area, and wherein the first and second signal lines are asymmetrical with respect to a virtual central line through a center of the first area in the first direction.
US10910455B2
Disclosed is a display apparatus. The display apparatus includes a substrate, a first wiring part on the substrate, a first insulation layer on the first wiring part, a microchip on the first insulation layer, a second wiring part on the microchip, and an organic light emitting device on the second wiring part. The microchip includes a first surface and a second surface opposite to each other, a first pad part on the first surface, and a second pad part on the second surface. The first pad part is connected to the first wiring part, and the second pad part is connected to the second wiring part.
US10910454B2
A display device includes a substrate, regions on the substrate each including a transparent first and a second regions, one or more light-emitting elements disposed in the second region, and a circular polarizing pattern disposed in front of the pixel regions. Each of the one or more light-emitting elements includes a reflective electrode and a transparent electrode layered one above the other, and a light-emitting film provided between the transparent electrode and the reflective electrode. The light-emitting film is configured to emit light in response to electric current supplied between the reflective electrode and the transparent electrode. The circular polarizing pattern covers the entire reflective electrode when seen from the front of the display device. At least a part of the first region is located within a gap in the circular polarizing pattern when seen from the front of the display device.
US10910450B2
A chip on film package structure including a flexible film and a chip is provided. The flexible film includes a main body and a first wing body. The main body includes a main bonding portion configured to be bonded to a first substrate. The first wing body includes a first extending part and a first bent part. The first extending part is extended from a side of the main body. The first bent part is configured to be bent to a second substrate and having a first wing bonding portion. The first wing bonding portion is configured to be bonded to the second substrate. The first substrate and the second substrate are stacked on top of each other. The chip mounted on and electrically connected to the main body. A display device is also provided.
US10910445B2
A disclosed display device includes first electrodes, a second electrode, an organic layer arranged between the first electrodes and the second electrode, and an insulating film configured to cover at least a side face of each of the first electrodes. The insulating film includes a first insulating layer configured to cover at least a part of the side face of each of the first electrodes, and a second insulating layer configured to cover the side face. The first insulating layer is arranged between the side face and the second insulating layer, and includes a first part and a second part whose density is lower than a density of the first part.
US10910443B2
An organic electroluminescence display device includes a first electrode, a first light emitter on the first electrode, the first light emitter including a first light emitting layer, a first charge generation layer disposed on the first light emitter, a second light emitter on the first charge generation layer, the second light emitter including a second light emitting layer, and a second electrode on the second light emitter. The first light emitter includes a first electron injection enhancing layer on the first light emitting layer. The second light emitter includes an electron injection suppressing layer on the second light emitting layer, the electron injection suppressing layer having electron mobility less than that of the first electron injection enhancing layer.
US10910439B1
A tandem solar cell comprises a back subcell; a front subcell; and an interconnecting layer of Cr/MoO3 between the back subcell and the front subcell and connecting the two subcells in series. The front subcell may comprise a carbazole-thienyl-benzothiadiazole based polymer and the back subcell may comprise an isoindigo-based polymer. A method for making a tandem solar cell comprises a) providing a substrate layer; b) applying a layer of PCDTBT:PC71BM to the substrate layer; c) applying a bilayer of chromium and MoO3 to the PCDTBT:PC71BM layer; d) applying a layer of P(T3-iI)-2:PC71BM on the bilayer of chromium and MoO3; and e) applying a Ca and Al electrode layer on the top.
US10910435B2
A method of forming an electrical device that includes forming an amorphous semiconductor material on a metal surface of a memory device, in which the memory device is vertically stacked atop a first transistor. The amorphous semiconductor material is annealed with a laser anneal having a nanosecond duration to convert the amorphous semiconductor material into a crystalline semiconductor material. A second transistor is formed from the semiconductor material. The second transistor vertically stacked on the memory device.
US10910434B2
A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/−10%) and less than or equal to 60 Angstroms (+/−10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/−10%) or 30-50 atomic percent (+/−10%).
US10910425B2
A solid-state image sensor including a semiconductor layer having a light incident side, a support substrate positioned on an opposite side of the light incident side of the semiconductor layer, photoelectric conversion elements formed two-dimensionally in the semiconductor layer, light reflection structures formed on a surface of the support substrate which faces toward the semiconductor layer, and positioned such that the light reflection structures face the photoelectric conversion elements, respectively, and an interlayer insulating layer formed between adjacent ones of the light reflection structures. The light reflection structures include a light transmission layer and a reflective metal that covers a surface of the light transmission layer opposite to a surface facing the semiconductor layer, and the reflective metal has a concave curved surface facing the photoelectric conversion elements.
US10910422B2
An image sensor package includes a substrate, an image sensor chip disposed on the substrate, and an external force absorbing layer disposed between the substrate and the image sensor chip and having a first surface and a second surface opposite to the first surface. The image sensor package further includes an adhesive layer configured to bond the second surface of the external force absorbing layer to the substrate. The adhesive layer has a first modulus, and the external force absorbing layer has a second modulus different from the first modulus.
US10910419B2
An image sensor is provided and includes a semiconductor substrate having a first conductivity type, a photoelectric conversion region in the semiconductor substrate and having a second conductivity type, an oxide semiconductor pattern adjacent to a first surface of the semiconductor substrate, and a transfer gate on the first surface and adjacent to the photoelectric conversion region and the oxide semiconductor pattern.
US10910414B1
An integrated ultraviolet (UV) detector includes a silicon carbide (SiC) substrate, supporting metal oxide field effect transistors (MOSFETs), and PN Junction photodiodes. The MOSFET includes a first drain/source implant in the SiC substrate and a second drain/source implant in the SiC substrate. The P-N junction photodiodes include a blanket oxide over the silicon carbide substrate and the gate, an implant extending into the silicon carbide substrate, and an opening extending through the blanket oxide layer down to the silicon carbide substrate on one side of the gate of the P-N junction photodiode.
US10910407B2
A high-performance semiconductor device is provided. The semiconductor device includes a transistor, an insulating film over the transistor, an electrode, and a metal oxide over the insulating film. The transistor includes a first gate electrode, a first gate insulating film over the first gate electrode, an oxide over the first gate insulating film, a source electrode and a drain electrode electrically connected to the oxide, a second gate insulating film over the oxide, and a second gate electrode over the second gate insulating film. The electrode includes a region in contact with the insulating film. The first gate insulating film is in contact with the insulating film. The thicknesses of the insulating film over the second gate electrode, the insulating film over the source electrode, and the insulating film over the drain electrode are substantially the same, and the insulating film includes excess oxygen.
US10910402B1
A three-dimensional AND type flash memory and a manufacturing method thereof includes steps below is provided. A stack structure includes a first insulating layer and a first sacrificial layer is formed. A first pillar structure through the stack structure includes a second insulating layer and a second sacrificial layer surrounded by thereof is formed. A second pillar structure through the stack structure includes a channel layer and an insulating pillar surrounded by thereof is formed. The second sacrificial layer is located on both sides of the channel layer. The first sacrificial layer is removed. A lateral opening exposing a portion of the second insulating layer and the channel layer is formed. A gate insulating layer surrounding the exposed second insulating layer and channel layer is formed in the lateral opening. A gate layer is filled in the lateral opening. A conductive layer is used to replace the second sacrificial layer.
US10910392B2
A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars.
US10910391B2
A semiconductor memory device comprises a substrate, first semiconductor films extending in a first direction crossing a surface of the substrate and arranged in a second direction and in a third direction, a conductive layer which covers peripheral faces of the first semiconductor films on a cross-section crossing the first direction, and a contact which extends in the first direction. Here, when straight lines disposed at equal intervals in the second direction on the cross-section and perpendicular to the second direction are defined as first to third straight lines, a first number of the first semiconductor films are provided on the first straight line, a second number less than the first number of the first semiconductor films are provided on the second straight line, a third number less than the second number of the first semiconductor films are provided on the third straight line.
US10910386B2
According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; and forming a bit line structure in the trench.
US10910385B2
A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.
US10910377B2
Laterally-diffused-metal-oxide-silicon (LDMOS) devices, integrated circuits including LDMOS devices, and methods for fabricating the same are provided. An exemplary LDMOS device includes a substrate having a surface, a gate structure overlying the surface and a channel region in the substrate below the gate structure, and a drain region in the substrate. The LDMOS device further includes a surface insulator region disposed between the gate structure and the drain region at the surface of the substrate and a dielectric block different from the surface insulator region and located over the surface insulator region. Also, the LDMOS device includes a field effect structure. The field effect structure includes a field plate disposed over and distanced from the surface of the substrate. The field effect structure also includes a conductive structure coupled to the field plate and extending from the field plate toward the dielectric block.
US10910370B2
Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a channel region protruding from a substrate in a vertical direction, a first source/drain region, and a second source/drain region. The first source/drain region may vertically overlap the channel region. The first and second source/drain regions may contact a first portion and a second portion of the channel region, respectively, and a third portion of the channel region between the first and second portions may include a first channel region extending longitudinally in a first horizontal direction that is perpendicular to the vertical direction and a second channel region extending longitudinally in a second horizontal direction that is perpendicular to the vertical direction and traverses the first horizontal direction. The integrated circuit devices may also include a gate structure on opposing vertical sides of the channel region.
US10910368B1
A circuit structure including a first gate structure, a first multi-connected channel layer and a second transistor is provided. The first gate structure has a first extension direction, and the first gate structure has a first end and a second end opposite to each other. The first gate structure is fully surrounded by the first multi-connected channel layer, and a plane direction of the multi-connected channel layer is perpendicular to the first extension direction. The first gate structure and the first multi-connected channel layer form a first transistor. The second transistor is disposed in the first multi-connected channel layer. A second gate structure or a channel of the second transistor is electrical connected to the first multi-connected channel layer.
US10910366B2
A three-dimensional stacked integrated circuit (3D SIC) for implementing an artificial neural network (ANN) having a memory die having an array of memory partitions. Each partition of the array of memory partitions is configured to store parameters of a set of neurons. The 3D SIC also has a processing logic die having an array of processing logic partitions. Each partition of the array of processing logic partitions is configured to: receive input data, and process the input data according to the set of neurons to generate output data.
US10910359B2
A transistor includes a first insulator over a substrate; a first oxide thereover; a second oxide in contact with at least part of the top surface of the first oxide; a first conductor and a second conductor each in contact with at least part of the top surface of the second oxide; a third oxide that is over the first conductor and the second conductor and is in contact with at least part of the top surface of the second oxide; a second insulator thereover; a third conductor which is over the second insulator and at least part of which overlaps with a region between the first conductor and the second conductor; and a third insulator which is over the third conductor and at least part of which is in contact with the top surface of the first insulator. The thickness of a region of the first insulator that is in contact with the third insulator is less than the thickness of a region of the first insulator that is in contact with the first oxide.
US10910351B2
An optoelectronic component includes a carrier including a mounting face, wherein at least one optoelectronic semiconductor chip configured to emit electromagnetic radiation is arranged above the mounting face, a molding material is arranged above the mounting face, the optoelectronic semiconductor chips are embedded into the molding material, a cavity is formed in the molding material, the cavity is empty, radiation emission faces of the optoelectronic semiconductor chips are not covered by the molding material, the cavity is accessible through an opening in the molding material, and an opening face of the opening is smaller than a sum of all radiation emission faces of the optoelectronic semiconductor chips.
US10910345B2
The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a first die, a second die, a first redistribution layer, a second redistribution layer, a first interconnect structure, and a second interconnect structure. The second die is stacked on the first die, the first redistribution layer is disposed between a first substrate of the first die and a second ILD layer of the second die, and the second redistribution layer is disposed on a second substrate of the second die. The first interconnect structure connects the first redistribution layer to one of first metal lines of the first die, and the second interconnect structure connects the second redistribution layer to one of the second metal lines in the second ILD layer.
US10910342B2
An example embodiment may include a method for placing on a carrier substrate a semiconductor device. The method may include providing a semiconductor substrate comprising a rectangular shaped assist chip, which may include at least one semiconductor device surrounded by a metal-free border. The method may also include dicing the semiconductor substrate to singulate the rectangular shaped assist chip. The method may further include providing a carrier substrate having adhesive thereon. The method may additionally include transferring to and placing on the carrier substrate the rectangular shaped assist chip, thereby contacting the adhesive with the rectangular shaped assist chip at least at a location of the semiconductor device. The method may finally include singulating the semiconductor device, while remaining attached to the carrier substrate by the adhesive, by removing a part of rectangular shaped assist chip other than the semiconductor device.
US10910341B1
First and second contacts are formed on first and second wafers from disparate first and second conductive materials, at least one of which is subject to surface oxidation when exposed to air. A layer of oxide-inhibiting material is disposed over a bonding surface of the first contact and the first and second wafers are positioned relative to one another such that a bonding surface of the second contact is in physical contact with the layer of oxide-inhibiting material. Thereafter, the first and second contacts and the layer of oxide-inhibiting material are heated to a temperature that renders the first and second contacts and the layer of oxide-inhibiting material to liquid phases such that at least the first and second contacts alloy into a eutectic bond.
US10910335B2
A light-emitting module includes a common carrier; a plurality of semiconductor devices formed on the common carrier, and each of the plurality of semiconductor devices including three semiconductor dies; a carrier including a connecting surface; a third bonding pad and a fourth bonding pad formed on the connecting surface; and a connecting layer. One of the three semiconductor dies includes a stacking structure; a first bonding pad; and a second bonding pad with a shortest distance less than 150 microns between the first bonding pad. The connecting layer includes a first conductive part including a first conductive material having a first shape; and a blocking part covering the first conductive part and including a second conductive material having a second shape with a diameter in a cross-sectional view. The first shape has a height greater than the diameter.
US10910328B2
Provided is a silicon wafer manufacturing method capable of reducing the warpage of the wafer occurring during a device process and allowing the subsequent processes, which have been suffered from problems due to severe warping of the wafer, to be carried out without problems and its manufacturing method. A silicon wafer manufacturing method according to the present invention is provided with calculating a target thickness of the silicon wafer required for ensuring a warpage reduction amount of a silicon wafer warped during a device process from a relationship between an amount of warpage of a silicon wafer and a thickness thereof occurring due to application of the same film stress to a plurality of silicon wafers having mutually different thicknesses; and processing a silicon single crystal ingot to thereby manufacture silicon wafers having the target thickness.
US10910323B2
The present disclosure provides a semiconductor package including a bottom package having a substrate, a radio-frequency (RF) die and a system-on-a-chip (SoC) die arranged on the substrate in a side-by-side manner, a molding compound covering the RF die and the SoC die, and an interposer over the molding compound. Connection elements and a column of signal interference shielding elements are disposed on the substrate. The connection elements surround the SoC die. The column of signal interference shielding elements is interposed between the RF die and the SoC die. A top package is mounted on the interposer.
US10910319B2
A back alignment mark on a surface of a semiconductor substrate is detected and a resist mask patterned into a circuit pattern corresponding to a surface element structure is formed on a back of the semiconductor substrate. Detection of the back alignment mark is performed by using a detector opposing the back of the semiconductor substrate and measuring contrast based on the intensity of reflected infrared light irradiated from the back of the semiconductor substrate. The back alignment mark is configured by a step formed by the surface of the semiconductor substrate and bottoms of trenches formed from the surface of the semiconductor substrate. A polysilicon film is embedded in the trenches. The back alignment mark has, for example, a cross-shaped planar layout in which three or more trenches are disposed in a direction parallel to the surface of the semiconductor substrate.
US10910307B2
Back end of line metallization structures and processes of fabricating the metallization structures generally include one or more metal filled via structures within a dielectric layer of an interconnect level, wherein at least one of the metal filled via structures includes a bulk metal and a metal alloy overlaying the bulk metal, wherein the bulk metal and metal alloy filled via is coupled to an active circuit.
US10910305B2
Embodiments of the invention include a microelectronic device that includes a substrate having transistor layers and interconnect layers including conductive layers to form connections to transistor layers. A capacitive bump is disposed on the interconnect layers. The capacitive bump includes a first electrode, a dielectric layer, and a second electrode. In another example, an inductive bump is disposed on the interconnect layers. The inductive bump includes a conductor and a magnetic layer that surrounds the conductor.
US10910298B2
An electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns, wherein the land bottom surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer. In one embodiment, a package body encapsulates the top surface of the insulating material and the electronic device, wherein the land bottom surfaces are exposed to the outside of the package body.
US10910287B2
A semiconductor package having a die with a sidewall protected by molding compound, and methods of forming the same are disclosed. The package includes a die with a first surface opposite a second surface and sidewalls extending between the first and second surfaces. A redistribution layer is formed on the first surface of each die. An area of the first surface of the die is greater than an area of the redistribution layer, such that a portion of the first surface of the die is exposed. When molding compound is formed over the die and the redistribution layer to form a semiconductor package, the molding compound is on the first surface of the die between an outer edge of the redistribution layer and an outer edge of the first surface. The molding compound is also on the sidewalls of the die, which provides protection against chipping or cracking during transport.
US10910279B2
A variable resistance memory device includes a memory unit including a first electrode, a variable resistance pattern and a second electrode sequentially stacked on a substrate, a first selection structure on the memory unit, a third electrode structure on the first selection structure, and an anti-fuse including a fourth electrode, a second selection structure and a fifth electrode structure sequentially stacked. The fourth electrode directly contacts the second selection structure, and a bottom of the fourth electrode is lower than a bottom of the second electrode.
US10910270B2
A manufacturing and packaging method for a semiconductor die is provided. The method prepares a wafer which has a seal-ring region, forms a first interlayer insulating film on the wafer, forms a metal wiring in the first interlayer insulating film, forms a second interlayer insulating film on the first interlayer insulating film, forms metal pads on the second interlayer insulating film, forms a passivation layer on the metal pads, removes a portion of the passivation layer in a region adjacent to the seal-ring region to expose the second interlayer insulating film, etches a portion of the second interlayer insulating film, forms a bump on the metal pads, removes the first interlayer insulating film and the second interlayer insulating film in the region adjacent to the seal-ring region by a laser grooving process, and dices the wafer into a first semiconductor die and a second semiconductor die.
US10910269B2
A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of cutting the wafer by using a cutting apparatus to thereby divide the wafer into individual device chips, and a pickup step of heating the polyester sheet, pushing up each device chip through the polyester sheet, and then picking up each device chip from the polyester sheet.
US10910266B2
A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.
US10910262B2
A method of selectively depositing a capping layer structure on a semiconductor device structure is disclosure. The method may include; providing a partially fabricated semiconductor device structure comprising a surface including a metallic interconnect material, a metallic barrier material, and a dielectric material. The method may also include; selectively depositing a first metallic capping layer over the metallic barrier material and over the metallic interconnect material relative to the dielectric material; and selectively depositing a second metallic capping layer over the first metallic capping layer relative to the dielectric material. Semiconductor device structures including a capping layer structure are also disclosed.
US10910257B2
A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si1-xGex, Si1-xCx, Si1-x-yGexSny, Si1-x-y-zGexSnyCz, Ge1-xSnx, group IIIA-nitrides, semiconductor oxides, and any combination thereof.
US10910250B2
The present disclosure relates to a method for mechanically separating layers, in particular in a double layer transfer process. The present disclosure relates more in particular to a method for mechanically separating layers, comprising the steps of providing a semiconductor compound comprising a layer of a handle substrate and an active layer with a front main side and a back main side opposite the front main side, wherein the layer of the handle substrate is attached to the front main side of the active layer, then providing a layer of a carrier substrate onto the back main side of the active layer, and then initiating mechanical separation of the layer of the handle substrate, wherein the layer of the handle substrate and the layer of the carrier substrate are provided with a substantially symmetrical mechanical structure.
US10910247B2
A substrate container including a casing, a rack, a casing holder, a casing lifting mechanism, a lid, and a lid holder. When holding of substrates with the rack shifts to holding of the substrates with the casing holder and the lid holder, the casing lifting mechanism moves the casing holder upward, whereby the casing holder moves the substrates upward. When the holding of the substrates with the casing holder and the lid holder shifts to the holding of the substrates with the rack, the casing lifting mechanism moves the casing holder downward, whereby the casing holder moves the substrates downward.
US10910243B2
A thermal management system comprising a fluid channel with a plurality of parallel first flow paths extending along a first level in a first thermal mass and a plurality of parallel second flow paths extending along a second level in a second thermal mass are described. Methods for controlling the temperature of a substrate or heater surface and fluid manifolds are also described.
US10910240B2
A first transfer robot carries a substrate into and out of a container. A second transfer robot receives and delivers the substrate from and to the first transfer robot, and carries the substrate into and out of a first processing portion through a first exit/entrance port. A third transfer robot receives and delivers the substrate from and to the second transfer robot, carries the substrate into and out of a second processing portion through a second exit/entrance port, and carries the substrate into and out of a third processing portion through a third exit/entrance port.
US10910231B2
A method of fabricating a semiconductor device includes forming a first etching pattern structure and a second etching pattern structure on a substrate. The first cell etching pattern structure has a top surface at a level that is different from that of a top surface of the second etching pattern structure. The method further includes forming a first spacer layer on the first etching pattern structure and the second etching pattern structure. The first spacer layer covers top and lateral surfaces of the first etching pattern structure and top and lateral surfaces of the second etching pattern structure. The method further includes performing a first etching process on the first spacer layer to form a first spacer and a second spacer. The first spacer layer is fully exposed during the first etching process of the first spacer layer.
US10910230B2
Provided is a semiconductor manufacturing apparatus including: a container in which a processing chamber is installed; a stage installed in the processing chamber and configured to hold a semiconductor substrate; a gas supply line configured to supply reactive gas to the processing chamber; and a vacuum line configured to exhaust the processing chamber, wherein the semiconductor substrate includes a high-k insulating film, and as the reactive gas, mixed gas including complex-forming gas forming a volatile organometallic complex by reacting with a metal element included in the high-k insulating film and complex stabilizing material gas that increases stability of the organometallic complex is supplied.
US10910229B2
A method capable of increasing a degree of freedom of process conditions that can be set in a plasma treatment while limiting deterioration in the electrical characteristics of a silicon or metal oxide film exposed to plasma, in performing the plasma treatment on a substrate. The method includes: processing a substrate on which a silicon or metal oxide film is formed, with plasma obtained by plasmarizing a process gas composed of a halogen compound; and subsequently, heating the substrate at a temperature of 450 degrees C. or higher in an inert gas atmosphere or a vacuum atmosphere in a state where the metal oxide film exposed to the plasma is exposed. Thus, deterioration in the characteristics of the oxide film caused by the plasma treatment are restored.
US10910228B2
Surface treatment processes for treating a workpiece with organic radicals are provided. In one example implementation, a method for processing a workpiece having a semiconductor material and a carbon containing layer (e.g., photoresist) can include a surface treatment process on the workpiece. The surface treatment process can include generating one or more species in a first chamber (e.g., a plasma chamber). The surface treatment process can include mixing one or more hydrocarbon radicals with the species to create a mixture. The surface treatment process can include exposing the carbon containing layer to the mixture in a second chamber (e.g., a processing chamber).
US10910223B2
A method includes etching a semiconductor substrate to form a first trench and a second trench. A remaining portion of the semiconductor substrate is left between the first trench and the second trench as a semiconductor region. A doped dielectric layer is formed on sidewalls of the semiconductor region and over a top surface of the semiconductor region. The doped dielectric layer includes a dopant. The first trench and the second trench are filled with a dielectric material. An anneal is then performed, and a p-type dopant or an n-type dopant in the doped dielectric layer is diffused into the semiconductor region to form a diffused semiconductor region.
US10910218B2
A SiC substrate (1) has an off angle θ°. A SiC epitaxial layer (2) having a film thickness of Tm μm is provided on the SiC substrate (1). Triangular defects (3) are formed on a surface of the SiC epitaxial layer (2). A density of triangular defects (3) having a length of Tm/Tan θ×0.9 or more in a substrate off direction is denoted by A. A density of triangular (3) defects having a length smaller than Tm/Tan θ×0.9 in the substrate off direction is denoted by B. B/A≤0.5 is satisfied.
US10910214B2
A method of manufacturing a semiconductor device includes: providing a substrate that includes a surface exposing a first film containing silicon, oxygen, carbon and nitrogen and having an oxygen atom concentration higher than a silicon atom concentration, which is higher than a carbon atom concentration, which is equal to or higher than a nitrogen atom concentration; and changing a composition of a surface of the first film so that the nitrogen atom concentration becomes higher than the carbon atom concentration on the surface of the first film, by supplying a plasma-excited nitrogen-containing gas to the surface of the first film.
US10910210B2
The present invention has as its object the provision of an ultraviolet sterilizer that can reduce ultraviolet light in a wavelength region of 230 to 300 nm, which is harmful to the human body, and can output effective light in a wavelength region of 200 to 230 nm with high emission intensity. The ultraviolet sterilizer of the present invention is an ultraviolet sterilizer comprising: an ultraviolet light source; a lamp storage chamber for storing the ultraviolet light source; and a light guiding part for guiding light from the ultraviolet light source, in which a band pass filter for reducing ultraviolet light in a wavelength region harmful to a human body is provided at least one of a position between the light guiding part and the lamp storage chamber and a position of a light outputting leading end of the light guiding part, and an inner surface of the light guiding part is formed from an ultraviolet absorbing member that absorbs the ultraviolet light in the wavelength region harmful to the human body.
US10910208B2
Systems and approaches for semiconductor metrology and surface analysis using Secondary Ion Mass Spectrometry (SIMS) are disclosed. In an example, a secondary ion mass spectrometry (SIMS) system includes a sample stage. A primary ion beam is directed to the sample stage. An extraction lens is directed at the sample stage. The extraction lens is configured to provide a low extraction field for secondary ions emitted from a sample on the sample stage. A magnetic sector spectrograph is coupled to the extraction lens along an optical path of the SIMS system. The magnetic sector spectrograph includes an electrostatic analyzer (ESA) coupled to a magnetic sector analyzer (MSA).
US10910193B2
An electron detector assembly configured for detecting electrons emitted from a sample irradiated by an electron beam, including a scintillator configured with a scintillator layer formed with a scintillating surface. The scintillator layer emits light signals corresponding to impingement of electrons upon the scintillating surface. A light guide plate is coupled to the scintillator layer and includes a peripheral surface. One or more silicon photomultiplier devices are positioned upon the peripheral surface, wherein one or more silicon photomultiplier devices are arranged perpendicularly or obliquely relative to the scintillating surface. The silicon photomultiplier device is configured to yield an electrical signal from an electron impinging upon the scintillator surface.
US10910173B2
A button restoring mechanism of an electronic device includes a housing, an adjustment button mounted on the housing, a bracket, and an elastic member. One side of the adjustment button protrudes within the housing. The bracket latches with the adjustment button. One end of the elastic member is fixed to one side of the bracket, and a second end of the elastic member abuts against a second side of the bracket. An elastic force of the elastic member drives the second side of the bracket to abut against a switch button within the housing.
US10910171B2
A switch device includes a substrate having at least one fixed contact and an inflow/outflow section provided with at least one through-hole, and a rubber contact to cover the substrate. The rubber contact includes at least one moving section disposed facing the respective at least one fixed contact, the moving section elastically deforming such that moving contacts corresponding to the respective fixed contacts are capable of contacting/separating, an in/out section disposed facing the inflow/outflow section and configured to form a space with the inflow/outflow section, a flow path section configured to form a flow path to connect the in/out section and the at least one moving section, and at least one chamber section having a space larger than a space occupying along representative length of the flow path section on a portion of the flow path section, and having strength such that a shape of the space is maintained.
US10910168B2
An electronic device is provided, which includes a substrate, a protruding pattern, a first conductive pattern, an insulating layer, and a second conductive pattern. The protruding pattern is disposed on the substrate. The first conductive pattern is disposed on the substrate and covers the protruding pattern. The insulating layer is disposed on the first conductive pattern. The insulating layer includes an opening overlapping at least a portion of the protruding pattern. The second conductive pattern is disposed on the insulating layer. The second conductive pattern is connected to the first conductive pattern through the opening.
US10910165B2
A process for forming high surface area graphene structures includes: depositing at least one metal on a surface of silicon carbide; heating the at least one metal and the silicon carbide to cause at least one of the metals to react with a portion of the silicon carbide to form silicide regions extending into an unreacted portion of the silicon carbide and graphene disposed between the silicide regions and the unreacted portion of the silicon carbide; and removing the silicide regions to provide a silicon carbide structure having a highly irregular surface and a surface layer of graphene.
US10910164B2
The present invention relates to a biaxially stretched polypropylene film for capacitor. The biaxially stretched polypropylene film for capacitor of the present invention can suppress an increase in tan δ and a decrease in the electrostatic capacitance even when the capacitor is used at a high voltage and an elevated temperature for a long duration.
US10910161B2
A capacitor component includes a humidity resistant layer formed on a portion of the external surface of a body on which an external electrode is not formed, and further includes a humidity resistant layer disposed inside the external electrode, to improve humidity resistance reliability. The capacitor component includes an opening portion formed by removing a portion of the humidity resistant layer disposed inside the external electrode to improve electrical connection.
US10910157B2
An electronic component includes a multilayer capacitor, including a capacitor body, and a pair of external electrodes disposed on both ends of the capacitor body, respectively, and an interposer, including an interposer body, and a pair of external terminals disposed on both ends of the interposer body, respectively. The external terminals include bonding portions, mounting portions, and connection portions disposed to connect the bonding portions and the mounting portions to each other. Adhesives are provided between the external electrodes and the bonding portion. A height at which the adhesives fall along the connection portions of the external terminals is defined as t and a height of the interposer is defined as T, t/T satisfies 0.04≤t/T≤0.80.
US10910151B2
The present invention relates to a device for the contact-free inductive transfer of electrical energy from a first, preferably stationary system of a shifting device into a second system of the shifting device, which can be moved relative to the first system, comprising a magnetic circuit of a primary core, which is assigned to the first system and onto which a primary coil is wound, and a secondary core, which is assigned to the second system and onto which a secondary coil is wound. The secondary core is arranged so as to be capable of being shifted relative to the primary core along a shifting path, which preferably runs parallel to a shifting path of the shifting device. The primary core extends at least along the entire length of the shifting path. According to the invention, provision is made for the primary core to comprise at least one primary core gap, which is embodied along the entire longitudinal extension of the primary core. The invention further relates to a shifting device, in particular a linear shifting device, comprising such an energy transfer device as well as to a method for operating such a device.
US10910150B2
A reconfigurable coupled inductor is disclosed. In one embodiment, the reconfigurable coupled inductor comprises metal rings and switches coupled to the metal rings to control at least one inductor property (e.g., coupling coefficient) based on a closed (e.g., on) or open state (e.g., off) of each switch.
US10910146B2
A three-phase reactor includes an outer peripheral iron core for surrounding the outer periphery of the three-phase reactor, and at least three iron core coils, which are in contact with or coupled to the inner surface of the outer peripheral iron core. The at least three iron core coils includes iron cores and coils wound around the iron cores. Gaps, which can be magnetically coupled, are each formed between two adjacent ones of the iron cores. The three-phase reactor further includes a vibration suppressing structure part disposed in the vicinity of the gaps so as to reduce vibrations occurring at the gaps.
US10910142B1
A switching power converter includes a first and second switching device, an air core coupled inductor, and a controller. The air core coupled inductor includes a first winding electrically coupled to the first switching device and a second winding electrically coupled to the second switching device. The first and second windings are magnetically coupled. The controller is operable to cause the first and second switching devices to repeatedly switch between their conductive and non-conductive states at a frequency of at least 100 kilohertz to cause current through the first and second windings to repeatedly cycle, thereby providing power to an output port. The switching power converter may have a topology including, but not limited to, a buck converter topology, a boost converter topology, and a buck-boost converter topology.
US10910139B1
A common mode choke assembly includes a main core, a shunt core, and first and second two-piece bobbins. The main core has a generally rectangular main core body, and first and second core riser portions. The first and second core riser portions are connected to opposite ends of the main core body. The first core riser portion includes a first riser notch and the second core riser portion includes a second riser notch aligned with the first riser notch. The shunt core spans between and is positioned within the first and second riser notches. The first and second two-piece bobbins are positioned on opposite sides of the main core body adjacent to the first and second core riser portions. Each two-piece bobbin includes at least first and second end flanges, a passageway, and a mating surface. The assembly further includes a mounting header for receiving the main and shunt core.
US10910137B2
An electromagnetic positioning system (1), including a valve train adjustment system for combustion engines, including a bistable electromagnetic positioning device (2) having a positioning element (3) for interacting with a positioning partner, the positioning element being adjustable between a retracted position (E) and an extended position (A) along an axis of adjustment (A) and having permanent magnet means (5) at least in sections.
US10910132B2
The present invention is a superconducting wire including: a wire formed of a superconducting material; and a superconducting stabilization material disposed in contact with the wire, in which the superconducting stabilization material is formed of a copper material which contains: one or more types of additive elements selected from Ca, Sr, Ba, and rare earth elements in a total of 3 ppm by mass to 400 ppm by mass; a balance being Cu and inevitable impurities, and in which a total concentration of the inevitable impurities excluding O, H, C, N, and S which are gas components is 5 ppm by mass to 100 ppm by mass.
US10910127B2
In a method of chemical vapor deposition (CVD) growth of a polycrystalline diamond film in a CVD reactor, a gas mixture of gaseous hydrogen and a gaseous hydrocarbon is introduced into the CVD reactor. A plasma formed from the gas mixture is maintained above a surface of a conductive substrate disposed in the CVD reactor and causes a polycrystalline diamond film to grow on the surface of the conductive substrate. A temperature T at the center of the polycrystalline diamond film is controlled during growth of the polycrystalline diamond film. The CVD grown polycrystalline diamond film includes diamond crystallites that can have a percentage of orientation along a [110] diamond lattice direction≥70% of the total number of diamond crystallites forming the polycrystalline diamond film.
US10910123B2
Methods for isolating Pb and/or Pb isotopes from various sources are provided. Compositions comprising Pb and/or Pb isotopes free of certain amounts of various contaminants are also provided.
US10910118B2
An electrical penetration assembly for a nuclear reactor vessel, mountable in an aperture of a nuclear reactor vessel, includes a penetration body including first and second ends to be positioned, respectively, inside and outside the vessel; a sealed electrical connector providing a first seal for the electrical penetration assembly, the sealed connector insulating the penetration body at the first end; a feed-through carrier flange having a plurality of unitary electrical feed-throughs, each unitary feed-through allowing a single electrical conductor to pass therethrough, thereby ensuring continuity of the electrical connections, each unitary feed-through being individually insulated by an individual insulator providing a second seal, the unitary feed-throughs insulating the penetration body at the second end; and an anti-ejection device formed by the engagement between a narrowed portion provided at each unitary feed-through and a shoulder that is larger than the narrowed portion and provided on each of the electrical conductors.
US10910109B2
A computing system can execute a correlation model for a library of health assertions to configure a correlation value for each health assertion. The correlation value comprises a correlation between knowledge associated with the health assertion and known health outcomes of individuals in a control group who have also provided responses to the health assertions. The computing system provides a health trivia session for users and based at least in part on the performance of the user, generates a mortality outcome profile that is used to classify the user in an underwriting class.
US10910103B2
Embodiments described herein provide various examples of a surgical procedure analysis system for extracting an actual procedure duration that involves actual surgical tool-tissue interactions from a total procedure duration of a surgical procedure. In one aspect, the process for generating the haptic feedback signal includes the steps of: obtaining the total procedure duration of the surgical procedure; receiving a set of operating room (OR) data from a set of OR data sources collected during the surgical procedure; analyzing the set of OR data to detect a set of non-surgical events during the surgical procedure that do not involve surgical tool-tissue interactions; extracting a set of durations corresponding to the set of events; and determining the actual procedure duration by subtracting the combined set of durations corresponding to the set of events from the total procedure duration.
US10910096B1
A computing system for displaying patient data in augmented reality (AR) is disclosed herein. An AR computing device worn by a healthcare worker captures an image indicative of a patient by way of a camera comprised by the AR computing device. The AR computing device transmits the image to an electronic health records application (EHR) executing on a server computing device. The EHR retrieves patient data for the patient responsive to identifying the patient based upon the image. Responsive to receiving the patient data from the EHR, the AR computing device presents the patient data on an AR display comprised by the AR computing device. The patient data is overlaid on the AR display with a view of surroundings of the healthcare worker as perceived by the healthcare worker through the AR display.
US10910090B2
A medium storing a program that causes a computer to execute a process includes receiving first pieces of terminal identification information and a request for updating second pieces of terminal identification information included in management targets to the first pieces of terminal identification information, comparing the second pieces of terminal identification information with the first pieces of terminal identification information, transmitting information including at least one of a first number of terminals to be excluded from the management targets by executing a update regarding the request, a second number of terminals to be added to the management targets by executing the update, and a third number of terminals that are included in the management targets before and after executing the update, and when receiving an instruction to execute the update regarding the request, updating the second pieces of terminal identification information to the first pieces of terminal identification information.
US10910073B2
A memory system includes a nonvolatile memory configured to execute one of a plurality of read operations, including a first read operation and a second read operation, and a memory controller configured to issue a read command to the nonvolatile memory to cause the nonvolatile memory to execute one of the plurality of read operations. The memory controller is configured to receive a read request, estimate a reliability level of a result of a read operation to be executed by the nonvolatile memory to read data from a physical address specified in the read request, select one of the first and second read operations to be executed first in a read sequence corresponding to the read request by the nonvolatile memory based on the estimated reliability level, and instruct the nonvolatile memory to execute the selected read operation.
US10910063B2
A memory device having an improved threshold voltage distribution includes: a memory block including a plurality of memory cells; a peripheral circuit configured to perform an erase operation on the memory block; and control logic configured to: control the peripheral circuit to suspend the erase operation in response to a suspend command received from an external source, determine an erase state of the plurality of memory cells by using a plurality of erase state verify voltages in response to a resume command received subsequently to the suspend command, and determine a level of an erase voltage to be applied to the memory block and an erase voltage applying time for which the erase voltage is to be applied based on the determination result.
US10910061B2
Numerous embodiments of programming systems and methods for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
US10910058B2
A memory array includes (a) multiple memory cells arranged into a plurality of bytes, (b) a separate word line connected to each byte, and (b) multiple shared source lines, each connected to at least two bytes, such that each byte in the array is addressable by a separate word line and by the shared source line. Due to this memory array architecture, a program operation on a first byte applies a shared source line voltage on a non-selected second byte (with an inhibit voltage applied to bit lines connected to the second byte), which creates a disturb condition that corresponds with a diagonal (or row) program disturb condition in a conventional memory array. The use of the shared source lines may reduce the required number of source line drivers, which reduces the overhead area of the memory array, and at same time, allow backward compatibility of traditional byte-alterable EEPROM.
US10910057B2
A memory array includes strings that are configured to store keywords and inverse keywords corresponding to keys according to content addressable memory (CAM) storages schemes. A read circuit performs a CAM read operation over a plurality of iterations to determine which of the keywords are matching keywords that match a target keyword. During the iterations, a read controller biases word lines according to a plurality of modified word line bias setting that are each modified from an initial word line bias setting corresponding to the target keyword. At the end of the CAM read operation, the read controller detects which of the keywords are matching keywords, even if the strings are storing the keywords or inverse keywords with up a certain number of bit errors.
US10910055B2
The present invention provides a semiconductor device that can reduce the power consumption, including: a plurality of search memory cells arranged in a matrix; a plurality of match lines provided corresponding to each memory cell row to determine match/mismatch between data stored in the search memory cell and search data; a plurality of match line retention circuits provided corresponding to each of the match lines; a storage unit for storing information relating to the state of each of the match lines; and a selection circuit for selectively activating the match line retention circuits based on the information stored in the storage unit.
US10910049B2
A sub-word line circuit having a phase driver circuit to provide a first phase signal and a second phase signal. The sub-word line circuit includes a sub-word line driver circuit having a pull-up circuit configured to receive the first phase signal and a global word line signal. The pull-up circuit is further configured to drive a local word line to follow the global word line signal when the first phase signal is at a first value and isolate the local word line from the global word line signal when the first phase signal is at a second value. The sub-word line circuit also includes a processing device that sets the first phase signal to the first value prior to the global word line signal entering an active state and sets the first phase signal to the second value only after the global word line signal has entered a pre-charge state.
US10910047B2
A storage device includes a memory device configured to perform a read operation on a selected word line among a plurality of word lines, and a memory controller configured to control the memory device to: perform the read operation, perform a read retry operation on the selected word line, by changing a read voltage level, when the read operation fails, and perform an additional read retry operation on the selected word line, by changing the read voltage level and an application time of voltages related to the read operation, depending on whether the selected word line is a set word line, when the read retry operation fails.
US10910037B2
Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.
US10910028B2
A memory device includes a bank that includes first memory cells connected to a first column selection line and second memory cells connected to a second column selection line, a first column decoder that selects the first memory cells by transmitting a first column selection signal in a first direction through the first column selection line, and a second column decoder that selects the second memory cells by transmitting a second column selection signal in a second direction opposite to the first direction through the second column selection line. The first column decoder includes a first register that stores a first fail column address of the first memory cells, and a second register that stores a second fail column address of the second memory cells.
US10910023B2
A semiconductor storage device includes a sense amplifier configured to read and program data in memory cells, a first latch circuit to store read data or program data, a second latch circuit to store the first data transferred from the first latch circuit or the second data before the second data is transferred into the first latch circuit, an input/output circuit to output the first data stored in the second latch circuit and to transfer the second data received thereby to the second latch circuit, and a control circuit. Upon receiving a read command while the control circuit is performing a program operation on program data stored in second latch circuit, the control circuit interrupts the program operation to perform the read operation and resumes the program operation on the program data in response to a resume write command sequence that does not include the program data.
US10910012B1
According to one embodiment, a first decoding circuit calculates likelihood information by executing Viterbi decoding using a parameter for normalizing a branch metric on a signal sequence read from a magnetic disk. The second decoding circuit generates a first bit data sequence by iterative decoding using the likelihood information, and executes a check using a parity check matrix on the first bit data sequence. The control circuit causes the first decoding circuit and the second decoding circuit to repeatedly execute decoding, and updates the parameter in accordance with a check result obtained every time the decoding by the first decoding circuit and the second decoding circuit is executed. An acquisition circuit acquires numerical information corresponding to the number of bit errors included in the first bit data sequence obtained when the number of times of executions of the decoding is equal to a first value.
US10909996B2
An autocorrelation calculation unit 21 calculates an autocorrelation RO(i) from an input signal. A prediction coefficient calculation unit 23 performs linear prediction analysis by using a modified autocorrelation R′O(i) obtained by multiplying a coefficient wO(i) by the autocorrelation RO(i). It is assumed here, for each order i of some orders i at least, that the coefficient wO(i) corresponding to the order i is in a monotonically increasing relationship with an increase in a value that is negatively correlated with a fundamental frequency of the input signal of the current frame or a past frame.
US10909991B2
A computer-implemented method for verifying identity of a speaker is proposed. A low dimensional p-vector based on a speech of the speaker is extracted from the generated high dimensional speaker model and is then compared with the stored specific speaker's p-vector obtained previously during the enrollment process. The resulting biometric score is then used to determine whether to verify the speaker, or not.
US10909988B2
An electronic device includes a display, wherein the display is configured to present a user interface, wherein the user interface comprises a coordinate system. The coordinate system corresponds to physical coordinates. The display is configured to present a sector selection feature that allows selection of at least one sector of the coordinate system. The at least one sector corresponds to captured audio from multiple microphones. The sector selection may also include an audio signal indicator. The electronic device includes operation circuitry coupled to the display. The operation circuitry is configured to perform an audio operation on the captured audio corresponding to the audio signal indicator based on the sector selection.
US10909981B2
A method of controlling a device includes controlling a processor by a mobile terminal to acquire a voice instruction of a user, controlling an artificial intelligence (AI) module, in accordance with a mapping relationship collection which is between a preset voice command and an instruction code combination information, and an acquired voice instruction, to determine the instruction code combination information corresponding to the acquired voice instruction, where the acquired voice instruction has a plurality of instruction codes and transmission sequence of the instruction codes, and controlling the processor to transmit the instruction codes to a target device in accordance with the transmission sequence, where each of the instruction codes is used to instruct the target device to execute an operation corresponding to each of the instruction codes.
US10909978B2
Technologies for secure storage of utterances are disclosed. A computing device captures audio of a human making a verbal utterance. The utterance is provided to a speech-to-text (STT) service that translates the utterance to text. The STT service can also identify various speaker-specific attributes in the utterance. The text and attributes are provided to a text-to-speech (TTS) service that creates speech from the text and a subset of the attributes. The speech is stored in a data store that is less secure than that required for storing the original utterance. The original utterance can then be discarded. The STT service can also translate the speech generated by the TTS service to text. The text generated by the STT service from the speech and the text generated by the STT service from the original utterance are then compared. If the text does not match, the original utterance can be retained.
US10909966B2
An active noise reduction device includes a standard signal generator, adaptive filters, a control sound emitter, and an error signal detector. The standard signal generator generates a standard signal including harmonics of a fundamental frequency correlated with the control target sound. The adaptive filters each generates corresponding one of harmonic components of a control signal based on the standard signal. The adaptive filters each is for corresponding one of the harmonics. The control sound emitter emits a control sound based on the control signal. The error signal detector collects residual noise left over after interference between the control target sound and the control sound, and detects an error signal based on the residual noise. Each of the adaptive filters includes a step size determiner. The step size determiner sets the step size parameter based on a frequency variation in the corresponding one of the harmonic components of the standard signal.
US10909954B2
A carbon fiber sound board is disclosed with breaks in the fibers to improve the sound quality and timber of the carbon fiber instrument.
US10909948B2
A ubiquitous auto calibration device is provided, which includes microcontroller unit, flex bus, image receiver image processing module, and an image output unit. The microcontroller unit is provided for receiving the electronic signal and performing a self-adjusting process to the electronic signal. The flex bus is connected with the microcontroller unit, and is provided for transmitting the electronic signal to the image processing module after performing the self-adjusting process. The image receiver is provided for receiving the image signal from the image receiving interface. The image processing module is provided for performing an image calibration process to the image signal, so that the image signal can obey the color temperature standard, Gamma value, uniformity and color gamut standards when the panel outputs the image signal. The image output unit is connected with the panel and is provided for transmitting the electronic signal which is adjusted by the self-adjust process and the image signal which is adjusted by the image calibrating process, such that the panel can perform calibration process according to the electronic signal by the self-adjusting process and output the image signal processed by the image calibrating process.
US10909934B2
A display device includes first and second pixel areas spaced apart from each other so that corresponding scan lines are separate from each other, a first non-pixel area at a periphery of the first pixel area, a second non-pixel area at a periphery of the second pixel area and opposite to the first non-pixel area with at least one pixel area interposed therebetween, first scan lines in the first pixel area, second scan lines in the second pixel area, a first scan driver in the first non-pixel area and connected to the first scan lines, a second scan driver in the second non-pixel area and connected to the second scan lines, first wires in the first non-pixel area and connected to the first scan driver, second wires in the second non-pixel area and connected to the second scan driver; and connecting wires connecting the first wires and second wires.
US10909932B2
A display apparatus includes: a display panel configured to display an image based on input image data; a gate driver configured to output a gate signal to the display panel; a data driver configured to output a data voltage to the display panel; and a power voltage generator configured to generate a power voltage and output the power voltage to cause an image to display on the display panel. The power voltage has a response speed that varies according to the input image data.
US10909926B2
A pixel circuit for an electronic display may include a memory to store a digital data signal indicative of a value within a data range. The pixel circuit may also include a light-emitting diode to emit light based at least in part on the digital data signal. The pixel circuit may also include an initialization transistor to initialize the pixel circuit before the light-emitting diode emits light and a driving transistor to activate based at least in part on the digital data signal.
US10909922B2
An electro-optical device includes one unit circuit provided corresponding to an intersection between one scanning line and one data line, another unit circuit provided corresponding to an intersection between the one scanning line and another data line or an intersection between another scanning line and the one data line or an intersection between another scanning line and another data line, and an electro-optical element configured to be driven by using the one unit circuit or the another unit circuit.
US10909910B2
A display apparatus and control method thereof are provided. The display apparatus including: a display configured to display an image; a backlight unit including a plurality of light sources configured to emit light to a screen of the display; an image processor configured to divide an input image into a plurality of blocks, identify target brightness for each block, and adjust a control value of each of the plurality of light sources based on priority of each of the plurality of light sources; and a driver configured to drive the plurality of light sources based on the control value. Thus, the duty for controlling the quality of light from the light source is identified considering the duty of the light source corresponding to an area of which previously identified priority is high, and thus dimming control is possible taking effects of light diffusion from adjacent neighboring light sources into account.
US10909902B2
Display systems with a single plate optical waveguide and independently adjustable micro display arrays and related methods are provided. A method includes coupling: a first light portion received from the first micro display array to a first input grating region of the optical waveguide, a second light portion received from the second micro display array to a second input grating region of the optical waveguide, and a third light portion received from the third micro display array to a third input grating region of the optical waveguide. The method further includes directing: a first diffracted portion of the first light portion to a first expansion grating, a second diffracted portion of the second light portion to a second expansion grating, and a third diffracted portion of the third light portion to a third expansion grating. The method further includes using a single output grating outputting combined light.
US10909901B2
A pixel arrangement includes a plurality of first groups of sub-pixels arranged in a first direction, each first group including first sub-pixels and third sub-pixels arranged alternately. A plurality of second groups of sub-pixels are arranged in the first direction, each second group including third sub-pixels and second sub-pixels alternately arranged. The first groups and the second groups are alternately arranged in a second direction intersecting the first direction. The first groups and the second groups are arranged to form a plurality of third groups of sub-pixels arranged in the second direction and a plurality of fourth groups of sub-pixels arranged in the second direction. The third groups and the fourth groups are alternately arranged in the first direction, each third group including first sub-pixels and third sub-pixels alternately arranged, each fourth group including third sub-pixels and second sub-pixels alternately arranged.
US10909898B2
An image display device includes an image data conversion unit that performs conversion processing of input image data and a display unit that displays a plurality of subframes, in one frame period. In the image data conversion unit, the conversion processing is performed in a manner that, for each pixel, a hue and a saturation of the input image data and a hue and a saturation of driving image data in an HSV color space are held to be respectively equal to each other, color components of the driving image data are set to have the same value when the saturation of the input image data is equal to the minimum saturation, and when the saturation of the input image data is equal to the maximum saturation, the color components of the input image data are multiplied by the same value, and then the input image data is compressed.
US10909895B2
The present invention provides a correction system (1) in which a control circuit (40) of a display panel (2) generates unevenness correction data to be used for correcting display unevenness. The correction system includes a signal source (11), an imaging device (12), and a control device (13). The signal source outputs a signal for displaying a prescribed reference image on the display panel. The imaging device captures the reference image displayed on the display panel on the basis of the signal from the signal source and generates a captured image. The control device generates unevenness correction data for the display panel on the basis of the captured image. The control device generates unevenness correction data (51, 52) having a plurality of mutually different formats (F1, F2) for the display panel (S15A, S15B), and records the same in a storage unit (21) of the display panel (S16).
US10909891B2
A signage system comprising a first panel and a second panel arranged in a substantially parallel configuration, wherein portions of the first panel and second panel are kept apart at a predetermined distance by a plurality of spacers, thereby providing a space between the first panel and second panel that can enhance the visibility of designs on the first panel and second panel.
US10909890B1
A display system includes a rectangular frame that is surrounded on four sides and is open on two opposed faces. Two banners are disposed to cover the two open faces to enclose a space within the frame. At least one light emitting device is connected to the frame and disposed within the space. The two banners are backlit by the at least one light emitting device when each is in its respective extended position.
US10909886B2
Disclosed is a starry sky reproducing sheet containing: N laminated light reducing sheets stuck together, each of which has homogeneous light reducing effects (where N is two or larger); the starry sky reproducing sheet containing, with M and L being two mutually different integers that are one or larger and N or smaller (M>L): L-layer transmission holes that are formed through L light reducing sheets stuck together, so that light beams pass therethrough; and M-layer transmission holes that are formed, through M light reducing sheets stuck together including the L light reducing sheets, at different positions from those of the L-layer transmission holes; wherein light beams incident on one face of the starry sky reproducing sheet pass through the L- and M-layer transmission holes while being attenuated at mutually different light reduction ratios to become L- and M-layer transmitted beams respectively which are visibly recognizable as transmitted-light stars having mutually different brightnesses.
US10909884B2
Disclosed is an electronically adjustable joint, and associated systems and methods. A joint position of a multiple-axis joint, e.g., a 3-axis joint, can be tracked, as the joint moves through two or more dimensions. In an illustrative embodiment, the joint can provide a mechanical equivalent of a physical joint, e.g., a shoulder, elbow, hip, or knee, which can accommodate motion in rotational angle and/or tilt angle. In some embodiments, the joint includes electronically adjustable friction. An illustrative application provide electronically adjustable joints for an aging simulation suit, wherein one or more joints can be controllably stiffened in selective ranges, such that a wearer of the suit can experience the effects of aging, arthritis and/or other ailments. In an illustrative embodiment, a sensor can use four discrete 2-axis magnetometers to calculate the position of the magnet on the arm of the joint, to continuously sense and track the angle of the joint. In some embodiments, the system includes a mechanism, e.g., a servo, which can controllably tighten a socket around a ball joint, wherein the system can controllably adjust friction on the joint.
US10909882B2
The present invention relates to a braille display and an electronic device including the same. The braille display according to an aspect of the present invention includes: a base configured to be provided as a perpendicularly polarized plate-shaped magnet and have through holes formed in a perpendicular direction according to a predetermined arrangement; pins configured to be respectively inserted in the through holes so that an upper end of each pin perpendicularly moves between a first position at which the pin protrudes from an upper surface of the base and a second position at which the pin is accommodated in one of the through holes, the pins expressing braille by means of a combination of individual pins located at the first position; and coils configured to be installed to be respectively wound around the pins and move the pins up and down by receiving current and interacting with the magnet.
US10909881B2
A system is provided including a styling tool configured to treat or shape a user's hair, and a client device configured to communicate with the styling tool and provide feedback to the user regarding a user's usage of the styling tool. The client device is configured to receive input information from the user regarding a desired result to be achieved using the styling tool, and to output guidance information on a method of using the styling tool to achieve the desired result.
US10909877B2
Provided is an information processing system that acquires normative behavior information serving as an interaction with a specific object by a user and an evaluation value corresponding to the normative behavior information, associates and registers the normative behavior information and the evaluation value in a behavior database, and performs control such that an evaluation value of specific behavior information acquired through the communication unit is calculated using the evaluation value corresponding to the normative behavior information in accordance with a comparison result of comparing the specific behavior information with normative behavior information corresponding to the specific behavior information registered in the behavior database, an emotion value of the user is calculated on the basis of the calculated evaluation value, and the calculated emotion value is transmitted to an information processing device corresponding to the user who is a provision source of the specific behavior information.
US10909876B2
Disclosed is a spray paint simulator and training aid including a mock paint sprayer, a trigger sensor of the mock paint sprayer, a head-mounted display unit, a motion tracking system for tracking a position and an orientation of the mock paint sprayer and the head-mounted display unit, a computer running software operable to display a virtual object and a virtual paint sprayer on the head-mounted display and, in response to an input from the trigger sensor, simulate the accumulation of paint on the virtual object, wherein the simulating the accumulation of paint includes generating a plurality of vectors extending between the virtual paint sprayer and the virtual object within a dispersion pattern.
US10909875B2
A method for determining an effect of a simulated obstacle on a main rotor induced velocity of a simulated rotorcraft in a simulation, comprising: receiving an aircraft airspeed of the simulated rotorcraft and a height above ground for the simulated rotorcraft; generating a line of sight vector having a source position located on the simulated rotorcraft, a direction and a given length; determining a distance between the simulated obstacle and the simulated rotorcraft using the line of sight vector, the distance being at most equal to the given length of the line of sight vector; determining an induced airflow velocity using the distance between the simulated obstacle and the simulated rotorcraft, the aircraft airspeed and the height above ground, the induced airflow velocity being caused by a downwash recirculation flow generated by the simulated obstacle; and outputting the induced airflow velocity.
US10909856B2
A method of selecting, by a terminal of a wireless communication system, a mode of communication to be used to exchange data with the base stations of the wireless communication system. The mode of communication being selected from among at least two different modes of communication associated with different respective geographical zones. The terminal receiving a surveillance message transmitted by an aircraft, the surveillance message includes information on the position of the aircraft. The terminal estimating the geographical zone in which the terminal is situated, as a function of the aircraft position information extracted from the received surveillance message. The mode communication is selected as a function of the estimated geographical zone of the terminal.
US10909847B1
Constructing a noise pollution map for an area includes a first subset of users performing initial noise recordings in the area using audio devices, using machine learning to provide classification of noises in the initial noise recordings, a second subset of users, larger than the first subset of users, capturing noise in the area using audio devices, creating summaries of noises using the classification to classify noises captured by the second subset of users, and aggregating the summaries to construct the noise pollution map of the area. The audio devices may include headsets, smart speakers, smart television sets, and/or computers. The summaries of noises may be created using software that is installed locally on devices of the second subset of users. The summaries may include source information, amplitude and frequency characteristics, duration, parameters of a corresponding one of the audio devices, user location, surroundings, and/or user movement information.
US10909842B2
An apparatus to generate a user-defined crosswalk comprises a processor to receive an input from a user to request a crosswalk across a roadway at a selected location and a memory coupled to the processor to store information regarding the crosswalk. The processor is to transmit the request to one or more vehicles using the roadway, and to receive a response indicating whether the crosswalk request is accepted such that the one or more vehicles are to stop to allow the user to cross the roadway using the crosswalk at the selected location in the event the crosswalk request is accepted.
US10909833B2
A method for geo-location services is described. In one embodiment, the method includes tracking incidents that occur within a predetermined geographic area in relation to a subscription service, upon receiving a request for a list of incidents in relation to the predetermined geographic area, generating a notification comprising the requested list of incidents, and sending the notification to one or more subscribers within the predetermined geographic area.
US10909832B2
Various arrangements are presented for monitoring a resident of a residence. A confidence assessment may be performed based on a plurality of smart home devices in the residence. The residence may be identified as eligible for monitoring of the resident based on the confidence assessment. A learning process may be performed to create an ordinary behavior model. Data that is received from the plurality of smart home devices may be monitored to identify data indicative of behavior considered unusual based on the ordinary behavior model.
US10909817B2
Multiple different game symbol weighting sets are defined for selection in a given play of a reel-type game. Each game symbol weighting set defines a probability of each reel strip in the reel-type game landing at each particular stop position for that reel strip. By providing multiple different game symbol weighting sets, certain game symbols such as special themed game symbols may be favored for one or more plays of the game to increase the chance of hitting winning symbol combinations using that game symbol.
US10909809B2
Various aspects described for implementing skill-based, wager-based gaming techniques via computer networks, including one or more casino gaming networks. The skill-based, wager-based game may include a non-wager based gaming portion and a wager-based gaming portion. One or more players are able to concurrently engage in continuous game play of the non-wager based gaming portion during execution of wager-based gaming events which are automatically triggered based on events which occur during play of the non-wager based gaming portion. Payouts for a given wager-based game event outcome may include both monetary payouts and non-monetary payouts.
US10909806B2
Systems and methods for operating an adapted skill wagering interleaved game are disclosed. An adapted skill wagering game is provides a entertainment game and a gambling game. The entertainment game is provided by an entertainment system and is managed by a game world operating system. The gambling game is provided by a real credit operating system. The entertainment system also provides a game world interface that uses game world variable that describe a game state of the entertainment game to determine when a gambling event is triggered. In response to a determination that a gambling event being triggered, the game world interface of the entertainment system sends a trigger to the real credit operating system to perform a gambling event in the gambling game. The real credit operating system then performs the gambling event and resolves any wagers on the outcome of the gambling event.
US10909802B2
A gambling hybrid game with dynamic wager updating is disclosed. The gambling hybrid game includes an entertainment system engine that provides an entertainment game to a user, a real world engine that provides gambling games to one or more users, and a game world engine that monitors the entertainment game and provides gambling games when appropriate. The gambling hybrid game during the course of game play may dynamically update a wager amount to be placed on a gambling event in the gambling game.
US10909795B2
A computer-implemented method comprises: committing a transaction amount t of a transaction with a commitment scheme to obtain a transaction commitment value T, the commitment scheme comprising at least a transaction blinding factor r_t; encrypting a combination of the transaction blinding factor r_t and the transaction amount t with a public key PK_B of a recipient of the transaction; and transmitting the transaction commitment value T and the encrypted combination to a recipient node associated with the recipient for the recipient node to verify the transaction.
US10909789B2
A cam lock for cabinets, drawers, drug cabinets, credenzas, sliding doors, lockers, mail boxes and other door type applications is compact in size, fits an existing cam lock opening and provides electronic access via a keypad or other electronic access. Using batteries, such as AAA size batteries or smaller, the lock has electronics that release a lock turn knob or handle when the correct code is entered. Preferably a set of electronic contacts is included at an accessible position on the lock housing to allow both master access and power jumping with a common manager's implement, for situations of lost codes and/or battery failure. In a particular embodiment the lock is long, narrow and low in profile so as to fit on the margin of a steel or wood file cabinet, compatible with the cam lock opening already provided. The locks, NFC-enabled, can be used in securing delivery boxes to enable delivery access, when authorized.
US10909788B2
Cameras capture time-stamped images of predefined areas (zones) and assets (objects). Behaviors and actions of persons are tracked in the images with respect to the zones and the objects based on rules. Persons are identified when the behaviors or actions indicate that the persons are attempting to access a particular zone or a particular object. Multifactor authentication is performed on the persons based on the rules and access to the particular zone or the particular object is granted or denied. All access attempts along with the corresponding images associated with the access attempts are logged for auditing.
US10909777B2
An example method includes receiving, at a computing system, a first user input from a user interface during operation of a vehicle and responsive to receiving the first user input, determining a time of reception for the first user input. The method further includes receiving a first set of parameters from the vehicle that correspond to a first parameter identifier (PID). The method also includes determining a time of reception for each parameter, and based on the time of reception for the first user input and the time of reception for each parameter of the first set of parameters, determining a first temporal position for an indicator configured to represent the first user input on a graph of the parameters corresponding to the first PID. The method further includes displaying, on a display interface, the graph of the parameters corresponding to the first PID with the indicator in the first temporal position.
US10909776B2
The invention disclosed in this application is a device to individually test irrigation sprinkler heads. The invention is comprised of a cabinet with a water reservoir and submersible pump. The submersible pump is located in water reservoir in the bottom of the cabinet. The top section of the cabinet is equipped with doors with transparent panels to observe the sprinkler head as it is being tested.
US10909763B2
A user interface enables a user to calibrate the position of a three dimensional model with a real-world environment represented by that model. Using a device's sensor, the device's location and orientation is determined. A video image of the device's environment is displayed on the device's display. The device overlays a representation of an object from a virtual reality model on the video image. The position of the overlaid representation is determined based on the device's location and orientation. In response to user input, the device adjusts a position of the overlaid representation relative to the video image.
US10909762B2
A computer-implemented technique is described herein for facilitating a user's interaction with digital content in a mixed reality environment. The technique involves: displaying digital content to the user in a mixed reality environment in one or more two-dimensional graphical pages, via a display device of a mixed reality device; receiving input information from one or more environment-sensing devices that capture movement of the user; and detecting, based on the input information, whether the user has performed a telltale gesture directed to a graphical page. Each such telltale gesture includes physical action(s) that a user might perform on a physical object, such as a physical piece of paper. If the gesture-detecting engine detects such a gesture, the technique updates the display device of the mixed reality device to show an appropriate outcome. The telltale gestures include a part-removing gesture, a moving gesture, and a page-flipping gesture, etc.
US10909760B2
An augmented reality system comprises one or more sensors configured for capturing a set of data indicative of an emotional state of a user of the augmented reality system, and a processor configured for discerning the emotional state of the user based at least in part on the captured set of data, and rendering the discerned emotional state on an avatar of the user. The avatar can be displayed as a virtual object when viewed through one or more augmented reality display systems.
US10909758B2
Systems and methods for generating three-dimensional models with correlated three-dimensional and two dimensional imagery data are provided. In particular, imagery data can be captured in two dimensions and three dimensions. Imagery data can be transformed into models. Two-dimensional data and three-dimensional data can be correlated within models. Two-dimensional data can be selected for display within a three-dimensional model. Modifications can be made to the three-dimensional model and can be displayed within a three-dimensional model or within two-dimensional data. Models can transition between two dimensional imagery data and three dimensional imagery data.
US10909755B2
A method of scanning a 3D object includes: receiving a user's input to perform a scanning operation via a user interface, and in response using a light projector, projecting structured light onto the surface of a physical object about target positions on the surface of the physical object; and recording a sequence of first images of at least a portion of the surface of the physical object including a light scatter region illuminated by the structured light being projected about the target positions on the surface of the physical object using a camera. A trained image processing network configured during training to output data comprising a representation of positions being estimates of the target positions on the surface of the physical object in response to receiving one or more first images can be used.
US10909749B2
Techniques for generating an arbitrary perspective of a composite object are disclosed. In some embodiments, a specification of an orthographic view of a composite object comprises combined orthographic views of a plurality of objects, and an arbitrary perspective of the composite object is at least in part generated by populating the arbitrary perspective of the composite object with pixels harvested from existing images of the plurality of objects.
US10909748B2
A projection device viewpoint image of a three-dimensional projection target is acquired, a three-dimensional model corresponding to the projection target is prepared as projection contents, the three-dimensional model is converted into a two-dimensional image that coincides with the projection device viewpoint image, and the two-dimensional image that coincides with the projector viewpoint image is projected to the projection target.
US10909737B2
Applying an image effect within an image processing application. An image processing application receives a selection of an image effect to be applied to an image. The image includes image layers, each of which has a layer property and is created based on an application of a first effect. The application selects a template from a set of predefined templates. The selection is based on the image effect and the template. The template includes template layers. The application matches each of the image layers to a corresponding template layer having a template property corresponding to the layer property. The application determines from the matching that no conflicts exist between the image layers and the template. The application merges the image layers with the template layers and applies the image effect.
US10909734B2
A data visualization method and apparatus, where the method includes displaying a first density distribution diagram on a first map, where the first density distribution diagram represents density distribution, in a region, of source locations of flow events whose destinations are located in a target reference region, and displaying a second density distribution diagram on a second map, where the second density distribution diagram represents density distribution, in a region, of destinations of flow events whose source locations are located in the target reference region. Hence, bidirectional density distribution associated with each other using the target reference region are displayed on two maps in a linked manner, thereby implementing visualization of bidirectional density distribution data.
US10909725B2
A system comprises an encoder configured to compress attribute information and/or spatial for a point cloud and/or a decoder configured to decompress compressed attribute and/or spatial information for the point cloud. To compress the attribute and/or spatial information, the encoder is configured to convert a point cloud into an image based representation. Also, the decoder is configured to generate a decompressed point cloud based on an image based representation of a point cloud.
US10909713B2
A location, dimension, and height of an object can be determined and measured using shadows. The object is located on a surface and an array of lights is mounted over the surface and shines on the object. The surface can be switchable between a translucent state and a transparent state. A colored shadow occurs based on the color of the light that shines on the object, where red, green, and blue are the typical colors used to provide shadows. A camera that is located below the surface captures an image of the shadows. The camera can be a color camera or a monochrome camera. The image is processed using thresholding to segment the different types of shadows that can occur. With the shadows, calculations can be made to determine the location, dimension, and height of the object.
US10909711B2
A method of determining a pose of an image capture device includes capturing an image using an image capture device. The method also includes generating a data structure corresponding to the captured image. The method further includes comparing the data structure with a plurality of known data structures to identify a most similar known data structure. Moreover, the method includes reading metadata corresponding to the most similar known data structure to determine a pose of the image capture device.
US10909709B2
A body measurement device and a method for controlling the same are disclosed. The body measurement device comprises a camera capturing a first image that includes an RGB image and a depth image; a display displaying a graphic image; and a controller estimating a user's pose based on the first image, controlling the camera to automatically capture a second image, which includes the user's body image in front of the camera, if the user's pose is a first pose, generating the user's body line image based on the captured second image, measuring the user's body size based on the generated body line image; and controlling the display to display the user's body size.
US10909704B2
There are several types of plenoptic devices and camera arrays available on the market, and all these light field acquisition devices have their proprietary file format. However, there is no standard supporting the acquisition and transmission of multi-dimensional information. It is interesting to obtain information related to a correspondence between pixels of a sensor of said optical acquisition system and an object space of said 10 optical acquisition system. Indeed, knowing which portion of the object space of an optical acquisition system a pixel belonging to the sensor of said optical acquisition system is sensing enables the improvement of signal processing operations. The notion of pixel beam, which represents a volume occupied by a set of rays of light in an object space of an optical system of a camera along with a compact format for storing such information is thus introduce.
US10909703B2
The present disclosure relates to an image processing method, an electronic device and a computer-readable storage medium. A method comprises: acquiring a wide-angle image and a non-wide-angle image acquired by a wide-angle acquisition apparatus and a non-wide-angle acquisition apparatus respectively, a view finding range of the wide-angle image including that of a non-wide-angle image; performing image matching between the wide-angle image and the non-wide-angle image to identify a first sub-image in the wide-angle image corresponding to the non-wide-angle image; cutting out edge images from the wide-angle image, which comprise at least a first edge sub-image and a second edge sub-image at two opposite sides of the first sub-image; stitching the edge images and the non-wide-angle image to obtain a stitched image, wherein the first edge sub-image and the second edge sub-image are stitched to corresponding sides of the non-wide-angle image, respectively; and outputting the stitched image for display.
US10909701B2
The present disclosure discloses a method, a data acquisition and image processing system and a non-transitory machine-readable medium for obtaining a super-resolved image of an object. The method comprises: obtaining a plurality of structured images of the object by structured light; determining, from the structured images, modulation information of each structured light that comprises spatial frequency, phase shift and modulation factor; initializing a sample image of the object according the structured images and initializing structured pattern of each structured light by the corresponding modulation information; and restoring the image with improved resolution by adjusting the sample image and the structured pattern iteratively.