US09425379B2
A piezoelectric element including a first electrode 60, a piezoelectric body layer 70, and a second electrode 80, in which a seed layer 65, which performs control such that the piezoelectric body layer 70 is preferentially oriented with respect to a specific crystal plane, is formed between the first electrode 60 and the piezoelectric body layer 70, and the seed layer 65 is formed from a composite oxide with a perovskite structure that includes at least Bi, Sr, Fe and Ti and an element ratio of Bi, Sr, Fe, and Ti in the seed layer satisfies the Formula (1) below. Bi:Sr:Fe:Ti=x·(1−y):y:1−z:z (1) (1.0≦x<1.3, 0
US09425377B2
A method for fabricating a tunnel junction includes depositing a first electrode on a substrate, depositing a wetting layer having a thickness of less than 2 nm on the first electrode, using atomic layer deposition (ALD) to deposit an oxide layer on the wetting layer, and depositing a second electrode on the oxide layer. The wetting layer and the oxide layer form a tunnel barrier, and the second electrode includes a superconductor.
US09425366B2
A light emitting device includes a substrate member, a light emitting element, a resin member, an insulating layer and a fluorescent material layer. The light emitting element is arranged on the substrate member. The resin member surrounds sides of the light emitting element, and has a top portion located higher than a light emission surface of the light emitting element. The insulating layer covers the light emission surface of the light emitting element and an outer wall surface and an inner wall surface of the top portion of the resin member. The fluorescent material layer covers a surface of the insulating layer.
US09425365B2
Lighting devices having highly luminescent quantum dots are described. In an example, a lighting apparatus includes a housing structure or a substrate. The lighting apparatus also includes a light emitting diode supported within the housing structure or disposed on the substrate, respectively. The lighting apparatus also includes a light conversion layer disposed above the light emitting diode. The light conversion layer includes a plurality of quantum dots. Each quantum dot includes an anisotropic nanocrystalline core having a first semiconductor material and having an aspect ratio between, but not including, 1.0 and 2.0. Each quantum dot also includes a nanocrystalline shell having a second, different, semiconductor material at least partially surrounding the anisotropic nanocrystalline core.
US09425352B2
Disclosed are a semiconductor device, a light emitting device, and a method of manufacturing the same. The semiconductor device includes a substrate, a plurality of rods aligned on the substrate, a metal layer disposed on the substrate between the rods, and a semiconductor layer disposed on and between the rods. Electrical and optical characteristics of the semiconductor device are improved due to the metal layer.
US09425348B2
In a group III nitride semiconductor device according to one aspect of the present invention, in a p-type group III nitride semiconductor region formed on a semi-polar plane substrate, the concentration of hydrogen (H) contained in the p-type group III nitride semiconductor region is 25% or less of the concentration of a p-type dopant therein, and the concentration of oxygen contained in the p-type group III nitride semiconductor region is 5×1017 atoms/cm3 or lower, and an angle between a normal axis of a primary surface of the semi-polar plane substrate and a c-axis of the semi-polar plane substrate is not lower than 45 degrees and not higher than 80 degrees or not lower than 100 degrees and not higher than 135 degrees in a waveguide axis direction of the group III nitride semiconductor device.
US09425340B2
To provide a solar cell having improved photoelectric conversion efficiency and a solar cell module. A solar cell (10) is provided with a photoelectric conversion portion (20), a light receiving surface electrode (21a) and a back surface electrode (21b). The light receiving surface electrode (21a) is arranged on the light receiving surface (20a) of the photoelectric conversion portion (20). The back surface electrode (21b) is arranged on the back surface (20b) of the photoelectric conversion portion (20). The back surface electrode (21b) includes metal film (21b1) and an electrical connection electrode (21b2). The metal film (21b1) at least partially covers the back surface (20b). The electrical connection electrode (21b2) is arranged on the metal film (21b1).
US09425337B2
A solar cell can include a built-in bypass diode. In one embodiment, the solar cell can include an active region disposed in or above a first portion of a substrate and a bypass diode disposed in or above a second portion of the substrate. The first and second portions of the substrate can be physically separated with a groove. A metallization structure can couple the active region to the bypass diode.
US09425336B2
Provided is a photo active layer for a solar cell or a light emitting diode and a fabricating method thereof. The photo active layer is formed by alternately stacking silicon quantum dot layers in which a plurality of silicon quantum dots containing conductive type impurities are formed in a medium, which is a silicon compound, and conductive layers, which are polycrystalline silicon layers, containing the same conductive type impurities as those of the silicon quantum dots.
US09425334B2
A picosecond laser beam shaping assembly is disclosed for shaping a picosecond laser beam for use in patterning (e.g., scribing) semiconductor devices. The assembly comprises a pulsed fibre laser source of picosecond laser pulses, a harmonic conversion element for converting laser pulses at a first laser wavelength having a first spectral bandwidth to laser pulses at a second laser wavelength having a second spectral bandwidth, and a beam shaping apparatus for shaping the laser beam at the second laser wavelength, the beam shaping apparatus having a spectral bandwidth that substantially corresponds to the second spectral bandwidth so as to produce a laser beam having a substantially rectangular cross-sectional profile.
US09425333B2
A device including a surface layer of a selected material in a predetermined pattern on a substrate surface. A groove or ridge arranged in the substrate surface includes a bottom or top face, respectively, and at least one side face sloping relative to the bottom or top face. The surface layer is deposited on a part of the substrate including the groove or ridge by vacuum chamber sputtering the selected material from a sputtering source while moving the substrate past the sputtering source in a direction substantially perpendicular to a sputtering main lobe direction and with a normal to the substrate surface substantially in a predefined angle with the main lobe direction. By uniformly etching away surface layer material deposited on the substrate by the sputtering until freeing a substantial part of the side face, the predetermined pattern becomes defined substantially by the bottom face or the top face.
US09425329B2
Disclosed herein are a rectifying device and a method of fabricating the same. The rectifying device includes a first electrode formed in a flat shape, an insulating layer deposited on the first electrode and a second electrode formed on a preset region of the insulating layer in a nanaopillar shape in a longitudinal direction to be asymmetrical to the first electrode, thereby increasing current flow.
US09425327B2
A junction field effect transistor cell of a semiconductor device includes a top gate region, a lateral channel region and a buried gate region arranged along a vertical direction. The lateral channel region includes first zones of a first conductivity type and second zones of a second conductivity type which alternate along a lateral direction perpendicular to the vertical direction. A pinch-off voltage of the junction field effect transistor cell does not depend, or only to a low degree depends, on a vertical extension of the lateral channel region.
US09425326B2
Described herein is a method for forming a vertical memory device (150) having a vertical channel region (113) sandwiched between a source region (109, 112) and a drain region (114). A charge trapping layer (106) is provided either side of the vertical channel region (113) and associated source and drain regions (109, 112, 114). The source region (109, 112) comprises a junction between a first region (109) comprising a first doping type with a first doping concentration and a second region (112) comprising a second doping type which is opposite to the first doping type and with a second doping concentration. The drain region (114) comprises the first doping type with a first doping concentration. In another embodiment, the drain region has two regions of differing doping types and concentrations and the source region comprises the first doping type with the first doping concentration.
US09425325B2
The present claimed subject matter is directed to memory device that includes substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric.
US09425322B2
A highly reliable semiconductor device having stable electric characteristics is provided by suppressing, in a transistor including an oxide semiconductor film, diffusion of indium into an insulating film in contact with the oxide semiconductor film and improving the characteristics of the interface between the oxide semiconductor film and the insulating film. In an oxide semiconductor film containing indium, the indium concentration at a surface is decreased, thereby preventing diffusion of indium into an insulating film on and in contact with the oxide semiconductor film. By decreasing the indium concentration at the surface of the oxide semiconductor film, a layer which does not substantially contain indium can be formed at the surface. By using this layer as part of the insulating film, the characteristics of the interface between the oxide semiconductor film and the insulating film in contact with the oxide semiconductor film are improved.
US09425321B2
A thin-film transistor includes an oxidic semiconductor channel, a metallic or oxidic gate, drain and source contacts and at least one barrier layer positioned between the oxidic semiconductor channel and the drain and source contacts to inhibit an exchange of oxygen between the oxidic semiconductor channel and the drain and source contacts.
US09425320B2
Provided is a thin film transistor on fiber and a method of manufacturing the same. The thin film transistor includes a fiber; a first electrode, a second electrode and a gate electrode formed on fiber; a channel formed between the first and second electrodes; an encapsulant encapsulating the fiber, the first, second, and gate electrodes, and an upper surface of the channel; and a gate insulating layer formed in a portion of the inner area of the encapsulant.
US09425319B2
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, an integrated circuit includes a semiconductor substrate. A first fin and a second fin are adjacent to each other extending from the semiconductor substrate. The first fin has a first upper section and the second fin has a second upper section. A first epi-portion overlies the first upper section and a second epi-portion overlies the second upper section. A first silicide layer overlies the first epi-portion and a second silicide layer overlies the second epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric spacer is formed of a dielectric material and spans the lateral gap. A contact-forming material overlies the dielectric spacer and portions of the first and second silicide layers that are laterally above the dielectric spacer.
US09425318B1
Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a stack overlying a substrate. The stack includes a silicon germanium layer and a silicon layer, where the silicon germanium layer has a first germanium concentration. The stack is condensed to produce a second germanium concentration in the germanium layer, where the second germanium concentration is greater than the first germanium concentration. A fin is formed that includes the stack, and a gate is formed overlying the fin.
US09425312B2
Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material.
US09425299B1
A cylindrical confinement electron gas confined within a two-dimensional cylindrical region can be formed in a vertical semiconductor channel extending through a plurality of electrically conductive layers comprising control gate electrodes. A memory film in a memory opening is interposed between the vertical semiconductor channel and the electrically conductive layers. The vertical semiconductor channel includes a wider band gap semiconductor material and a narrow band gap semiconductor material. The cylindrical confinement electron gas is formed at an interface between the wider band gap semiconductor material and the narrow band gap semiconductor material. As a two-dimensional electron gas, the cylindrical confinement electron gas can provide high charge carrier mobility for the vertical semiconductor channel, which can be advantageously employed to provide higher performance for a three-dimensional memory device.
US09425290B2
The present disclosure discloses a method of fabricating a semiconductor device. A fin structure is formed over a substrate. The fin structure contains a semiconductor material. A first implantation process is performed to a region of the fin structure to form a fin seed within the region of the fin structure. The fin seed has a crystal structure. The first implantation process is performed at a process temperature above about 100 degrees Celsius. A second implantation process is performed to the region of the fin structure to cause the region of the fin structure outside the fin seed to become amorphous. The second implantation process is performed at a process temperature below about 0 degrees Celsius. Thereafter, an annealing process is performed to recrystallize the region of the fin structure via the fin seed.
US09425286B2
Various source/drain stressors that can enhance carrier mobility, and methods for manufacturing the same, are disclosed. An exemplary source/drain stressor includes a seed layer of a first material disposed over a substrate of a second material, the first material being different than the second material; a relaxed epitaxial layer disposed over the seed layer; and an epitaxial layer disposed over the relaxed epitaxial layer.
US09425279B1
A semiconductor device having a reduced variation in threshold voltage includes a semiconductor substrate with a high dielectric-constant (high-k) layer deposited in a gate trench and on a semiconductor portion of the substrate. At least one workfunction layer has an arrangement of first and second workfunction granular portions on an upper surface of the high-k layer to define a workfunction of the semiconductor device. The arrangement of first and second workfunction granular portions define a granularity of the at least one workfunction layer. A gate contact material fills the gate trench, wherein the high-k layer has a concentration of oxygen vacancies based on the granularity of the at least one work function metal layer so as to reduce the variation in the threshold voltage.
US09425275B2
An integrated circuit chip includes a semiconductor substrate, a first back-end-of-line unit circuit that includes a first group of field effect transistors, a second gate-loaded unit circuit that includes a second group of field effect transistors. The first group of field effect transistors includes a first transistor and the second group of field effect transistors includes a second transistor. A bottom surface of a gate electrode of the first transistor extends closer to a bottom surface of the semiconductor substrate than does a bottom surface of a gate electrode of the second transistor.
US09425274B2
The semiconductor device structures and methods for forming the same are provided. The semiconductor device structure includes a metal gate over a substrate. A first spacer is formed over sidewalls of the metal gate and having a first height. A second spacer is formed over the sidewalls of the metal gate and having a second height. The first height is higher than the second height. The first spacer is farther from the sidewalls of the metal gate than the second spacer. In addition, the semiconductor device structure includes a dielectric layer formed over the substrate to surround the first spacer and the metal gate.
US09425273B2
A semiconductor chip region includes a first conductive structure (CS) that forms a gate electrode (GE) of a first transistor of a first transistor type (TT) and a GE of a first transistor of a second TT, a second CS that forms a GE of a second transistor of the first TT, a third CS that forms a GE of a second transistor of the second TT, a fourth CS that forms a GE of a third transistor of the first TT, and a fifth CS that forms a GE of a third transistor of the second TT. Diffusion terminals of the first and second transistors of the first TT are electrically connected. Diffusion terminals of the first and second transistors of the second TT are electrically connected. Diffusion terminals of the second and third transistors of both the first TT and second TT are electrically connected.
US09425269B1
Device structures for a bipolar junction transistor and methods for fabricating such device structures. An emitter structure is formed that has a semiconductor layer with a top surface defining a recess and a sacrificial layer comprised of a disposable material in the recess. A contact opening is formed that extends through one or more first dielectric layers to the sacrificial layer. After the contact opening is formed, the sacrificial layer is removed from the recess. Alternatively, the layer in the recess may be comprised of a non-disposable material that may occupy the recess at the time that a contact is formed in the contact opening.
US09425263B2
A method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first heating step of heating the silicon carbide substrate in an atmosphere of oxygen is performed. A second heating step of heating the silicon carbide substrate to a temperature of 1300° C. or more and 1500° C. or less in an atmosphere of gas containing nitrogen atoms or phosphorus atoms is performed after the first heating step. A third heating step of heating the silicon carbide substrate in an atmosphere of a first inert gas is performed after the second heating step. Thus, the silicon carbide semiconductor device in which threshold voltage variation is small, and a method for manufacturing the same can be provided.
US09425240B2
Embodiments of forming an image sensor with organic photodiodes are provided. Trenches are formed in the organic photodiodes to increase the PN-junction interfacial area, which improves the quantum efficiency (QE) of the photodiodes. The organic P-type material is applied in liquid form to fill the trenches. A mixture of P-type materials with different work function values and thickness can be used to meet the desired work function value for the photodiodes.
US09425237B2
Solid-state memory having a non-linear current-voltage (I-V) response is provided. By way of example, the solid-state memory can be a selector device. The selector device can be formed in series with a non-volatile memory device via a monolithic fabrication process. Further, the selector device can provide a substantially non-linear I-V response suitable to mitigate leakage current for the non-volatile memory device. In various disclosed embodiments, the series combination of the selector device and the non-volatile memory device can serve as one of a set of memory cells in a 1-transistor, many-resistor resistive memory cell array.
US09425232B2
An imaging device includes a first semiconductor layer having a first surface and a second surface and a first photodetector having a first implanted region formed in the first semiconductor layer and a pad formed over the first implanted region. The imaging device also includes a readout circuit disposed over the first surface of the first semiconductor layer. The readout circuit has a plurality of contact plugs facing the first surface of the first semiconductor layer. The imaging device further includes a second semiconductor layer disposed below the second surface of the first semiconductor, a second photodetector having a second implanted region formed in the second semiconductor layer, and a metalized via extending through the first semiconductor layer and the second semiconductor layer and electrically connecting the second implanted region to a second of the contact plugs of the readout circuit.
US09425231B2
An image sensor includes: a first inter-layer dielectric layer formed over a front side of a substrate including photoelectric conversion regions; isolation structures each of which penetrates through the first inter-layer dielectric layer and has a portion buried in the substrate; first metal lines formed over the first inter-layer dielectric layer to correspond to the photoelectric conversion regions; and an optical filter and a light condenser formed over a back side of the substrate.
US09425223B1
The present invention provides a manufacture method of a TFT substrate, and the method comprises steps of: 1, deposing a first metal layer (2) on a substrate (1); 2, coating a first photoresistor layer (3) and implementing gray scal exposure; 3, removing a part of the first metal layer (2) to form a gate (21) and a source/a drain (23); 4, implementing ashing process to the first photoresistor layer (3); 5, deposing an isolation layer (4); 6, removing a part of the first photoresistor area (3) and a part of the isolation layer (4); 7, forming an oxide semiconductor layer (5); 8, deposing a protecting layer (6); 9, coating a second photoresistor layer (7) and implementing gray scal exposure; 10, removing a part of the protecting layer (6); 11, implementing ashing process to the second photoresistor layer (7); 12, deposing a transparent conducting thin film (8); 13, removing a part of second photoresistor layer (7) and a part of the transparent conducting thin film (8); 14, forming a pixel definition layer (9); 15, forming photo spacers (10).
US09425219B2
An array substrate, a manufacturing method thereof and a display panel are provided. The array substrate includes: a substrate; and first pixel groups and second pixel groups which are disposed on the substrate and are alternately arranged to form a pixel array. Each first pixel group includes two first pixel units, each first pixel unit includes a first pixel electrode connected with a common electrode and a second pixel electrode connected with a drain electrode of a drive TFT of the first pixel unit. Each second pixel group includes two second pixel units, each second pixel unit includes a third pixel electrode connected with a drain electrode of a drive TFT of the second pixel unit and a fourth pixel electrode connected with the common electrode.
US09425215B2
The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is sensitive to heat, such as a plastic substrate or a plastic film substrate. Moreover, the invention provides a wireless processor, a wireless memory, and an information processing system thereof which transmit and receive power or signals wirelessly. According to the invention, an information processing system includes an element forming region including a transistor which has at least a channel forming region formed of a semiconductor film separated into islands with a thickness of 10 to 200 nm, and an antenna. The transistor is fixed on a flexible substrate. The wireless processor in which a high functional integrated circuit including the element forming region is formed and the semiconductor device transmit and receive data through the antenna.
US09425208B2
A vertical memory device includes a substrate including a cell region and a peripheral circuit region, the peripheral circuit region including a gate structure comprising a transistor, a plurality of channels on the cell region, each of the channels extending in a first direction that is vertical with respect to a top surface of the substrate, a plurality of gate lines stacked in the first direction and spaced apart from each other, the gate lines surrounding outer sidewalls of the channels, and a blocking structure between the cell region and the peripheral circuit region, wherein a height of the blocking structure is greater than a height of the gate structure in the peripheral region.
US09425197B2
A semiconductor device includes a P-channel DMOS transistor provided with an N-type gate electrode, a P-channel MOS transistor provided with a P-type gate electrode, and an N-channel MOS transistor provided with an N-type gate electrode. The N-type gate electrode of the P-channel DMOS transistor desirably has a first end portion that is located on a source side of the P-channel DMOS transistor, a second end portion that is located on a drain side of the P-channel DMOS transistor, and a P-type diffusion layer at the first end portion.
US09425184B2
Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material. The method further includes forming an epitaxial material with doped regions on the mesa structure and forming gate material over at least the plurality of fin structures. The method further includes planarizing at least the gate material such that the gate material and the epitaxial material are of a same height. The method further includes forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material.
US09425179B2
Chip packages and methods of manufacture thereof are described. In an embodiment, a method for manufacturing a chip package may include: providing a support structure including: a base; and a stage pivotably attached to the base, the stage having a surface facing away from the base; attaching a first die having at least one second die disposed thereon to the surface of the stage; pivotably tilting the stage; and after the pivotably tilting, dispensing an underfill over the first die and adjacent to the least one second die, the underfill flowing through a first standoff gap disposed between the first die and the at least one second die.
US09425178B2
A method includes forming a first plurality of Redistribution Lines (RDLs) over a carrier, and bonding a device die to the first plurality of RDLs through flip-chip bonding. The device die and the first plurality of RDLs are over the carrier. The device die is molded in a molding material. After the molding, the carrier is detached from the first plurality of RDLs. The method further includes forming solder balls to electrically couple to the first plurality of RDLs, wherein the solder balls and the device die are on opposite sides of the first plurality of RDLs.
US09425172B2
Lamps, luminaries or solid state lighting components are disclosed having multiple discrete light sources whose light combines to provide the desired emission characteristics. The discrete light sources are arranged in an array pursuant to certain guidelines to promote mixing of light from light sources emitting different colors of light. One embodiment solid state lighting component comprises a light emitting diode (LED) component having an array of LED chips having a first group of LED chips and one or more additional groups of LED chips. The array is arranged so that no two LED chips from said first group are directly next to one another in the array, that less than fifty percent (50%) of the LED chips in the first group of LEDs is on the perimeter of the array, and at least three LED chips from the one or more additional groups is adjacent each of the LED chips in the first group.
US09425171B1
One embodiment of the present invention sets forth a technique for packaging an integrated circuit die. The technique includes bonding a first surface of the integrated circuit die to a first substrate via a first plurality of solder bump structures and bonding a second substrate to a second surface of the integrated circuit die. The technique further includes bonding the first substrate to a third substrate via a second plurality of solder bump structures and, after bonding the first substrate to the third substrate, removing the second substrate from the second surface of the integrated circuit die. The technique further includes disposing a heat sink on the second surface of the integrated circuit die.
US09425169B2
A flexible stack package includes a first package and a second package. Each of the first and second packages includes a flexible layer, a chip embedded in the flexible layer, and a contact portion disposed on the chip to penetrate the flexible layer and exposed at a surface of the flexible layer. Each of the first and second packages includes a fixing portion and a wing portion. A first adhesion part is disposed between the fixing portion of the first package and the fixing portion of the second package to combine the first package with the second package. A first stretchable interconnector electrically connects or couples the contact portion of the first package to the contact portion of the second package.
US09425168B2
A stud bump structure, a package structure thereof and method of manufacturing the package structure are provided. The stud bump structure include a first chip; and a silver alloy stud bump disposed on the substrate, wherein the on-chip silver alloy stud bump includes Pd of 0.01˜10 wt %, while the balance is Ag. The package structure further includes a substrate having an on-substrate bond pad electrically connected to the on-chip silver alloy stud bump by flip chip bonding.
US09425161B2
An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.
US09425152B2
An EMI shielding package structure includes a substrate unit having a first surface with a die mounting area and a second surfaces opposite to the first surface, metallic pillars formed on the first surface, a chip mounted on and electrically connected to the die-mounting area, an encapsulant covering the chip and the first surface while exposing a portion of each of the metallic pillars from the encapsulant, and a shielding film enclosing the encapsulant and electrically connecting to the metallic pillars. A fabrication method of the above structure by two cutting processes is further provided. The first cutting process forms grooves by cutting the encapsulant. After a shielding film is formed in the grooves and electrically connected to the metallic pillars, the complete package structure is formed by the second cutting process, thereby simplifying the fabrication process while overcoming inferior grounding of the shielding film as encountered in prior techniques.
US09425150B2
An interconnect structure and a method of forming the interconnect structure are provided. Two wafers (and/or dies) are bonded together. A multi-via interconnect structure is formed extending from a backside of a first substrate to interconnect structures in the metallization layers on the first integrated circuit and the second integrated circuit. The multi-via interconnect structure may be formed by thinning a first substrate of a first wafer and forming a first opening through the first substrate. A second opening extends from the first opening to a first interconnect structure on the first wafer, and a third opening extends from the first interconnect structure on the first wafer to a second interconnect structure on the second wafer. The first, second, and third openings are filled with a conductive material, thereby forming a multi-via interconnect structure.
US09425147B2
A semiconductor device includes an interlayer insulating film; a wiring formed on the interlayer insulating film so as to protrude there from and made of a material having copper as a main component, the wiring having a thickness direction and having a cross sectional shape of an inverted trapezoid that becomes wider in width with distance away from the interlayer insulating film; and a passivation film formed so as to cover the wiring. The passivation film is made of a laminated film in which a first nitride film, an intermediate film, and a second nitride film are laminated in that order from the wiring side. The intermediate film is made of an insulating material differing from those of the first and second nitride films, and has a tapered portion having a cross sectional shape of a trapezoid that becomes narrower in width with distance away from the interlayer insulating film.
US09425144B2
Structure providing more reliable fuse blow location, and method of making the same. A vertical metal fuse blow structure has, prior to fuse blow, an intentionally damaged portion of the fuse conductor. The damaged portion helps the fuse blow in a known location, thereby decreasing the resistance variability in post-blow circuits. At the same time, prior to fuse blow, the fuse structure is able to operate normally. The damaged portion of the fuse conductor is made by forming an opening in a cap layer above a portion of the fuse conductor, and etching the fuse conductor. Preferably, the opening is aligned such that the damaged portion is on the top corner of the fuse conductor. A cavity can be formed in the insulator adjacent to the damaged fuse conductor. The damaged fuse structure having a cavity can be easily incorporated in a process of making integrated circuits having air gaps.
US09425143B2
Some novel features pertain to an integrated device package that includes a die, an electromagnetic (EM) passive device, an encapsulation layer covering the die and the EM passive device, and a redistribution portion coupling the die and the EM passive device. In some implementations, the EM passive device includes an electromagnetic (EM) passive device. The EM passive device includes a base layer, a via traversing the base layer, a pad coupled to the via, and at least redistribution layer configured to operate as electromagnetic (EM) passive component, where the redistribution layer is coupled to the pad. The redistribution portion of the EM passive device includes at least one redistribution layer that is configured to electrically couple the die to the EM passive device. The redistribution portion includes at least one redistribution layer that is configured as an electromagnetic (EM) shield.
US09425137B2
A wiring board includes multiple insulating layers including first, second, third, fourth and fifth insulation layers laminated in the order of the first, second, third, fourth and fifth insulation layers. The first insulation layer has a first conductor including plating, the second insulation layer has a second conductor including plating, the third insulation layer has a third conductor including conductive paste, the fourth insulation layer has a fourth conductor including plating, the fifth insulation layer has a fifth conductor including plating, and the first conductor, the second conductor, the third conductor, the fourth conductor and the fifth conductor are formed along the same axis and are electrically continuous with each other.
US09425136B2
A pillar structure for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled.
US09425133B2
An integrated circuit includes circuitry, a first conductor coupled to the circuitry, a conductive pad coupled to the first conductor, and a second conductor coupled to the conductive pad. The second conductor would be floating but for its coupling to the conductive pad. The second conductor may be spaced apart from the first conductor by a distance that is substantially equal to a width of a merged spacer that was formed from a merging of single sidewall spacers over a conductive material from which the first and second conductors were formed.
US09425128B2
A package includes an interposer, which includes a first substrate free from through-vias therein, redistribution lines over the first substrate, and a first plurality of connectors over and electrically coupled to the redistribution lines. A first die is over and bonded to the first plurality of connectors. The first die includes a second substrate, and through-vias in the second substrate. A second die is over and bonded to the plurality of connectors. The first die and the second die are electrically coupled to each other through the redistribution lines. A second plurality of connectors is over the first die and the second die. The second plurality of connectors is electrically coupled to the first plurality of connectors through the through-vias in the second substrate.
US09425125B2
An interposer is provided. The interposer includes a silicon substrate layer, a glass substrate layer, and at least one through interposer via. The silicon substrate layer is formed on top of the glass substrate layer. The interposer may also be known as a hybrid interposer because it includes two different types of substrate layers forming one interposer. The through interposer via is formed to go through the silicon substrate layer and the glass substrate layer. The interposer may be used for forming an integrated circuit package. The integrated circuit package includes multiple integrated circuits that are mounted on the interposer.
US09425122B2
A method for manufacturing an electronic component packages is provided, wherein a package precursor is provided, in which an electronic component is embedded in a sealing resin layer such that an electrode of the electronic component is exposed at a surface of the sealing resin layer. A combination of a formation process of a plurality of metal plating layers and a patterning process of the plurality of metal plating layers is provided to form a step-like metal plating layer, the formation process being performed by sequential dry and wet plating processes with respect to the package precursor, and the patterning process being performed by a patterning of at least two of the plurality of metal plating layers.
US09425109B2
A planarization method is provided. The planarization method includes providing a wafer, in which the wafer includes a work function layer, a surface layer formed on the work function layer and oxidized from the work function layer, and a planarization layer disposed on or above the surface layer, performing a chemical-mechanical planarization (CMP) process on the planarization layer, providing an incident light to a surface of the wafer under the CMP process, detecting absorption of the incident light by the surface layer; and stopping the CMP process in response to an increase in the detected absorption of the incident light.
US09425108B1
A method for preventing epitaxial growth in a semiconductor device is described. The method includes cutting the fins of FinFET structure to form a set of exposed fin ends. A set of sidewall spacers are formed on the set of exposed fin ends, forming a set of spacer covered fin ends. The set of sidewall spacers prevent epitaxial growth at the set of spacer covered fin ends. A semiconductor device includes a set of fin structures having a set of fin ends. A set of inhibitory layers are disposed at the set of fin ends to inhibit excessive epitaxial growth at the fin ends.
US09425106B1
A method includes forming a plurality of fins above a substrate. At least one dielectric material is formed above and between the plurality of fins. A mask layer is formed above the dielectric material. The mask layer has an opening defined therein. A portion of the at least one dielectric material exposed by the opening is removed to expose top and sidewall surface portions of at least a subset of the fins. An etching process is performed to remove the portions of the fins in the subset exposed by removing the portion of the at least one dielectric material.
US09425105B1
A semiconductor device includes at least one semiconductor fin on an upper surface of a semiconductor substrate, and at least one metal gate stack formed on the upper surface of the semiconductor substrate. One or more pairs of source/drain contact structures are formed on the upper surface of the semiconductor fin. Each source/drain contact structure includes a metal contact stack, a spacer, and a cap spacer. The metal contact stack is formed on the upper surface of the fin. The spacer is interposed between a contact sidewall of the metal contact stack and a gate sidewall of the at least one metal gate stack. The cap spacer is formed on an upper surface of the metal contact stack and has a cap portion disposed against the spacer such that the metal gate stack is interposed between the opposing source/drain contact structures.
US09425101B2
FinFET and fabrication method thereof. The FinFET fabrication method includes providing a semiconductor substrate; forming a plurality of trenches in the semiconductor substrate, forming a buffer layer on the semiconductor substrate by filling the trenches and covering the semiconductor substrate, and forming a fin body by etching the buffer layer. The FinFET fabrication method may further includes forming a insulation layer on the buffer layer around the fin body; forming a channel layer on the surface of the fin body; forming a gate structure across the fin body; forming source/drain regions in the channel layer on two sides of the gate structure; and forming an electrode layer on the source/drain regions.
US09425085B2
Structures, devices and methods are provided for fabricating memory devices. A structure includes: a first conductive line disposed in a first conductive layer; a first landing pad disposed in the first conductive layer and associated with a second conductive line disposed in a second conductive layer; and a second landing pad disposed in the first conductive layer and associated with a third conductive line disposed in a third conductive layer. The second conductive layer and the third conductive layer are different from the first conductive layer.
US09425080B2
Semiconductor nanoparticles are deposited on a top surface of a first insulator layer of a substrate. A second insulator layer is deposited over the semiconductor nanoparticles and the first insulator layer. A semiconductor layer is then bonded to the second insulator layer to provide a semiconductor-on-insulator substrate, which includes a buried insulator layer including the first and second insulator layers and embedded semiconductor nanoparticles therein. Back gate electrodes are formed underneath the buried insulator layer, and shallow trench isolation structures are formed to isolate the back gate electrodes. Field effect transistors are formed in a memory device region and a logic device region employing same processing steps. The embedded nanoparticles can be employed as a charge storage element of non-volatile memory devices, in which charge carriers tunnel through the second insulator layer into or out of the semiconductor nanoparticles during writing and erasing.
US09425078B2
Systems and methods for depositing film in a substrate processing system includes performing a first atomic layer deposition (ALD) cycle in a processing chamber to deposit film on a substrate including a feature; after the first ALD cycle, exposing the substrate to an inhibitor plasma in the processing chamber for a predetermined period to create a varying passivated surface in the feature; and after the predetermined period, performing a second ALD cycle in the processing chamber to deposit film on the substrate.
US09425074B2
A heat treatment apparatus performs a heat treatment on a plurality of target objects held by a holding unit while allowing an inert gas to flow upwardly in a vertical processing container with at least one heating unit provided in the vicinity of the processing container. The heat treatment apparatus includes: a main temperature control unit configured to control the heating unit; an inert gas passage through which the inert gas flows into the processing container; an inert gas heating unit installed in the inert gas passage and configured to heat the inert gas; a first temperature measuring unit installed in the inert gas heating unit; and a temperature controller configured to control the inert gas heating unit based on temperatures measured by the first temperature measuring unit.
US09425072B2
A method for fabricating a semiconductor device includes forming an etching target layer over a substrate including a first region and a second region; forming a hard mask layer over the etching target layer; forming a first etch mask over the hard mask layer, wherein the first etch mask includes a plurality of line patterns and a sacrificial spacer layer formed over the line patterns; forming a second etch mask over the first etch mask, wherein the second etch mask includes a mesh type pattern and a blocking pattern covering the second region; removing the sacrificial spacer layer; forming hard mask layer patterns having a plurality of holes by etching the hard mask layer using the second etch mask and the first etch mask; and forming a plurality of hole patterns in the first region by etching the etching target layer using the hard mask layer patterns.
US09425070B2
Disclosed herein is a semiconductor device, including: a mount body having a first principal surface on which a wiring pattern is formed; a semiconductor chip mounted above the principal surface of the mount body on which the wiring pattern is formed; an underfill material filled between the mount body and the semiconductor chip, thereby forming a fillet in an outer peripheral portion of the semiconductor chip; and an introduction portion formed outside a side portion, along which the fillet is formed so as to be longest, of four side portions which measure a chip mounting area, on the mount body, onto which the semiconductor chip is mounted, the introduction portion serving to introduce the underfill material between the mount body and the semiconductor chip.
US09425068B2
A method for manufacturing semiconductor device may include the following steps: performing an etching process to remove a sacrificial layer from a first composite structure, wherein the first composite structure includes a first substrate structure; performing a heat treatment to release a gas from the first composite structure; performing a cleaning process to remove an oxide layer from the first composite structure; and combining the first composite structure with a second composite structure that includes a second substrate structure and an electronic component positioned on the second substrate substructure, such that the first substrate structure is combined with the second substrate structure to form an enclosure structure that encloses the electronic component.
US09425066B2
A circuit substrate includes a dielectric layer and a plurality of conductive structures. The dielectric layer has a plurality of conductive openings, a first surface, and a second surface opposite to the first surface. Each of the conductive openings connects the first surface and the second surface. The conductive openings are respectively filled with the conductive structures. Each of the conductive structures is integrally formed and includes a pad part, a connection part, and a protruding part. Each of the connection parts is connected to the corresponding pad part and the corresponding protruding part. Each of the protruding parts has a curved surface that protrudes from the second surface. A process for fabricating the circuit substrate is also provided.
US09425060B2
A method for fabricating multiple layers of ultra narrow silicon wires comprises the steps of fabricating wet-etch masking layers of silicon; forming a Fin and source/drain regions located at both ends thereof by epitaxy; forming the multiple layers of ultra narrow silicon wires. The present invention has advantages in that: the atom layer depositing may define the position of the ultra narrow silicon wires accurately, having a good controllability; the anisotropic wet-etch for silicon is performed in a self-stop manner and has a large process window, so that the cross-section shape of the nanowires formed by wet-etch is uniform and smooth. The method to form multiple layers of wet-etch masks at the sidewalls of Fins, in which wet-etch masking layers are formed prior to the epitaxy of Fins is a simple process, so that the multiple sidewall wet-etch masking layers may be obtained by only one etching to the epitaxy window, regardless of the numbers of the wet-etch masking layers; a wire with a diameter less than 10 nm may be fabricated by virtue of the oxidation technology, and thus satisfies the small size devices; the TMAH solution, which is simple and safe to control, is used in the wet-etch for polysilicon, and metal ions are not introduced and thus suitable for the integrated circuit manufacturing process; the method according to the present invention is fully compatible with the planar transistor based on the bulk silicon, and thus the process cost is small.
US09425058B2
Methods of patterning a blanket layer (a target etch layer) on a substrate are described. The methods involve multiple patterning steps of a mask layer several layers above the target etch layer. The compound pattern, made from multiple patterning steps, is later transferred in one set of operations through the stack to save process steps.
US09425055B2
A semiconductor device includes a semiconductor substrate, a charge storage stack over a portion of the substrate. The charge storage stack includes a first dielectric layer, a layer of nanocrystals in contact with the first dielectric layer, a second dielectric layer over and in contact with the layer of nanocrystals, a nitride layer over and in contact with the second dielectric layer, and a third dielectric layer over the nitride layer.
US09425049B2
The present disclosure relates to a method for performing a self-aligned litho-etch (SALE) process. In some embodiments, the method is performed by forming a first cut layer over a substrate having a multi-layer hard mask with a first layer and an underlying second layer. A first plurality of openings, cut according to the first cut layer, are formed to expose the second layer at a first plurality of positions corresponding to a first plurality of shapes of a SALE design layer. A spacer material is deposited onto sidewalls of the multi-layer hard mask to form a second cut layer. A second plurality of openings, cut according to the second cut layer, are formed to expose the second layer at a second plurality of positions corresponding to a second plurality of shapes of the SALE design layer. The second layer is etched according to the first and second plurality of openings.
US09425035B2
A mass or mass to charge ratio selective ion trap is disclosed which directs ions into a small ejection region. A RF voltage acts to confine ions in a first (y) direction within the ion trap. A DC or RF voltage acts to confine ions in a second (x) direction. A quadratic DC potential well acts to confine ions in a third (z) direction within the ion trap. The profile of the quadratic DC potential well progressively varies along the second (x) direction.
US09425033B2
The invention provides methods and devices to pulse ions from an RF ion storage into the flight tube of a time-of-flight mass spectrometer. The pusher cell comprises essentially two parallel plates, both plates completely slotted into two electrically insulated halves. The four half plates can be supplied with RF voltages to form a two-dimensional quadrupole field in the center between the slits, or with DC voltages to form a homogeneous acceleration field to eject ions. The RF quadrupole field is not ideal, but sufficiently good to store ions, to damp the ions by an additional collision gas, and to form a fine thread of ions in the axis of the quadrupole field. The DC acceleration field is extremely homogeneous; slight distortions near the slits can be corrected by external electrodes. The ideal acceleration field results in a high mass resolution and the device does not show any mass discrimination.
US09425030B2
A photomultiplier tube having an ion suppression electrode positioned between a photocathode and an electron multiplying device in the photomultiplier tube is disclosed. The ion suppression electrode includes a grid that is configured to provide sufficient rigidity to avoid deformation during operation of the photomultiplier tube. The photomultiplier tube also includes a source of electric potential connected to the electron multiplying device and to the ion suppression electrode to provide a first voltage to the second electrode and a second voltage to the suppression grid electrode wherein the second voltage has a magnitude equal to or greater than the magnitude of the first voltage. A method of making the photomultiplier and a method of using it are also disclosed.
US09425028B2
A plasma processing apparatus includes an upper electrode arranged at a processing chamber and including a plurality of gas supplying zones, a branch pipe including a plurality of branch parts, an addition pipe connected to at least one of the branch parts, and a plurality of gas pipes that connect the branch parts to the gas supplying zones. The upper electrode supplies a processing gas including a main gas to the processing chamber via the gas supplying zones. The branch pipe divides the processing gas according to a predetermined flow rate ratio and supplies the divided processing gas to the gas supplying zones. The addition pipe adds an adjustment gas. A gas flow path of the gas pipe connected to the branch part to which the addition pipe is connected includes a bending portion for preventing a gas concentration variation according to an adjustment gas-to-main gas molecular weight ratio.
US09425027B2
Methods of affecting a material's properties through the implantation of ions, such as by using a plasma processing apparatus with a plasma sheath modifier. In this way, properties such as resistance to chemicals, adhesiveness, hydrophobicity, and hydrophilicity, may be affected. These methods can be applied to a variety of technologies. In some cases, ion implantation is used in the manufacture of printer heads to reduce clogging by increasing the materials hydrophobicity. In other embodiments, MEMS and NEMS devices are produced using ion implantation to change the properties of fluid channels and other structures. In addition, ion implantation can be used to affect a material's resistance to chemicals, such as acids.
US09425026B2
Systems and methods are provided for matching the impedance of a load to an impedance of a power generator. Embodiments include a matching network with a dynamically configurable component assembly array couplable to the variable impedance load and the RF power generator, wherein the component assembly array includes one or more tune and load electrical components. The component assembly array is adapted to be configured for each recipe step, and at least one of the electrical components is a variable impedance component adjustable to reduce RF energy reflected from the variable impedance load for each recipe step. Numerous other aspects are provided.
US09425024B2
A load simulator includes a passive element, two electrode plates that are connected to the passive element, and a bias applier. The bias applier is a coil spring, for example, and is provided between the two electrode plates. The bias applier biases at least one of the two electrode plates in a predetermined direction. The two electrode plates are disposed so as to be substantially parallel with each other, for example, and the bias applier biases the two electrode plates in the direction of separation from each other.
US09425023B2
An ion generator includes an arc chamber, a cathode that extends outward from the inside of the arc chamber in an axial direction and that emits a thermal electron into the arc chamber, a thermal reflector with a cylindrical shape provided around the cathode in a radial direction and extending in the axial direction, and a narrow structure configured to narrow a width in the radial direction of a gap between the cathode and the thermal reflector at a given position in the axial direction.
US09425022B2
Disclosed herein are a monochromator and a charged particle beam apparatus including the same. The monochromator may include a first electrostatic lens configured to have a charged particle beam discharged by an emitter incident on the first electrostatic lens, refract a ray of the charged particle beam, and include a plurality of electrodes and a second electrostatic lens spaced apart from the first electrostatic lens at a specific interval and configured to have a central axis disposed identically with a central axis of the first electrostatic lens, have the charged particle beam output by the first electrostatic lens incident on the second electrostatic lens, refract the ray of the charged particle beam, and comprise a plurality of electrodes. Accordingly, there is an advantage in that a charged particle beam can have an excellent profile even after passing through the monochromator.
US09425020B2
A miniaturized all-metal slow-wave structure includes: a circular metal waveguide; and metal electric resonance units provided in the circular metal waveguide; wherein the metal electric resonance unit provided in the circular metal waveguide includes a ring-shaped electric resonance metal plate with an electron beam tunnel provided on a center thereof, and a ring plate body of the ring-shaped electric resonance metal plate has two auricle-shaped through-holes symmetrically aside an axial-section; a main body of the auricle-shaped through-hole is a ring-shaped hole, two column holes extending towards a center of a circle are provided at two ends of the ring-shaped hole; the ring-shaped electric resonance metal plates are perpendicular to an axis and are provided inside the circular metal waveguide with equal intervals therebetween, external surfaces of the ring-shaped electric resonance metal plates are mounted on an internal surface of the circular metal waveguide.
US09425017B2
A manufacturing method of a complex type fusible link. The manufacturing method includes hollowing out a metal plate into a link-like conductor including a connecting plate and a terminal, cutting out the link-like conductor so as to separate the connecting plate and the terminal, forming, by insert molding, a block base including a cavity after setting the connecting plate and the terminal in a mold, and directly connecting a fusible element to an exposed portion of the connecting plate and an exposed portion of the terminal.
US09425012B2
There is provided an electromagnetic operation device for a vacuum circuit breaker, which controls by its electromagnetic operation, a speed of contact switching operation of a vacuum switch tube used in the vacuum circuit breaker, the electromagnetic operation device including a closing drive coil for the vacuum switch tube; and a first temperature sensor that measures a temperature surrounding the closing drive coil, wherein a current caused to flow through the closing drive coil is controlled based on the temperature measured by the first temperature sensor.
US09425008B1
A switch includes a switch housing, a button, a circuit board having at least one magnet sensor, and a magnet holder, including at least one magnet, movably mounted to the housing to move responsive to an actuation of the button. A vane interrupter in the switch includes a passage structure positioned proximate to each magnet sensor such that a respective magnet is movable at least partially within a passage defined by the passage structure, and a flange structure having a first flange and a second flange positioned on opposing ends of the passage structure, with the first flange positioned adjacent a portion of the magnet holder holding the magnet and with the second flange positioned adjacent a surface of the circuit board opposite a surface on which the at least one magnet sensor is positioned, such that the circuit board is positioned between the magnet holder and the second flange.
US09424986B2
A multi-function wireless power induction mousepad is composed of a lower soft pad, a foam pad and an upper soft pad, which is flexible and can be rolled for storage. A power module is embedded on the foam pad. The power module includes a power induction coil and a USB socket. The power module supplies power to a mouse having a charging induction coil or a cell phone to be charged. The present invention can cooperate with other peripheral devices, such as a display, a touch-control panel, an LED panel, a writing panel, electronic paper, electronic message board and the like, according to the demand of the user, providing a multi-function effect.
US09424985B2
A feed unit includes: a power transmission coil provided to perform power transmission with use of a magnetic field; a parallel LC resonance circuit including the power transmission coil; a series LC resonance circuit; an alternating-current signal generating section supplying the parallel LC resonance circuit and the series LC resonance circuit with an alternating-current signal used to perform the power transmission; and a control section controlling the alternating-current signal generating section with use of a predetermined control signal, the control section performing frequency control of the control signal to allow a circuit current that flows upon the power transmission to become smaller.
US09424979B2
A magnetic element includes a first magnetic core, a second magnetic core, an intermediate magnetic core, a first winding coil, and a second winding coil. The intermediate magnetic core is arranged between the first magnetic core and the second magnetic core. After the first magnetic core and the intermediate magnetic core are coupled with each other, a first winding space and a first air gap are defined. After the second magnetic core and the intermediate magnetic core are coupled with each other, a second winding space and a second air gap are defined. The first winding coil is disposed within the first winding space and arranged around the first air gap. The second winding coil is disposed within the second winding space and arranged around the second air gap. The first winding coil and the second winding coil are connected with each other in series.
US09424972B2
A solenoid for a vehicle starter includes at least one coil with a passage extending through the coil in an axial direction. The solenoid further includes a plunger configured to move in the axial direction within the passage. The plunger includes a cylindrical outer surface with a substantially uniform diameter and a circumferential notch. The cylindrical outer surface includes a first portion with a first diameter on one side of the circumferential notch, and a second portion with the first diameter on an opposite side of the circumferential notch. The circumferential notch includes a portion with a second diameter that is less than the first diameter.
US09424967B2
A varistor, or voltage-limiting composition has a polymer matrix and a particulate filler containing a partially conductive material applied to an electrically non-conductive carrier material. The carrier material has a lower density than the partially conductive material, so that the settling rate of the filler in the polymer matrix is reduced. The voltage-limiting composition can therefore also be used as a lacquer or for prepreg materials. A body which acts as a varistor may be produced using a composition of this kind by a method that includes annealing. The varistor may be used for surge arresters, in particular in medium-voltage systems, low-voltage systems, cable connections and cable fasteners.
US09424966B2
A method for forming an electrical connection structure part according to the present invention includes a step of covering, with an alloy body, a connection part between a first conductor part and a second conductor part, so as to form the electrical connection structure part. The first conductor part contains aluminum. The second conductor part has a surface covered with an ingredient containing nickel. The alloy body contains tin, silver, and nickel. The method further includes steps of: connecting the first conductor part and the second conductor part to each other to form the connection part; melting the alloy body; and dipping at least the connection part into the molten alloy body.
US09424957B1
A subdermal lighting apparatus with enhanced operational longevity, safety and biological compatibility with a user is provided. The subdermal lighting apparatus includes a housing unit to store a radioactive isotope, a phosphor layer affixed to an interior surface of the housing unit to interact with radiation emitted by the radioactive isotope to generate visible light, a radiation shielding layer disposed around the housing unit and able to permit the generated visible light to pass through, and a biologically safe layer disposed around the radiation shielding layer able to permit the generated visible light to pass through. The biologically safe layer serves as a barrier between the radiation shielding layer and biological tissue of the user, thereby enhancing user safety of the apparatus.
US09424956B2
This underwater electricity production module includes an elongated cylindrical box, which includes a reactor compartment and an electricity production unit. The reactor compartment includes a reservoir chamber and a dry chamber. A nuclear reactor is located in the dry chamber. The reservoir chamber forms a safety water storage reservoir. At least a radial wall of the reservoir chamber is in a direct heat exchange relationship with a marine environment that surrounds the cylindrical box. The nuclear reactor includes a nuclear boiler which includes a pressurizer connected through a depressurizing valve to the reservoir chamber.
US09424955B2
Embodiments of systems and methods for compressing plasma are described in which plasma pressures above the breaking point of solid material can be achieved by injecting a plasma into a funnel of liquid metal in which the plasma is compressed and/or heated.
US09424951B2
A sensor circuit is used to provide bit-cell read strength distribution of an SRAM array. A current-mirror circuit mirroring the bit-line current of an SRAM array is used to power the sensor circuit. A reference current representing nominal bit-cell read current is used as a reference. The current-mirror circuit senses the bit-line current. The current-mirror and the ring oscillator are not part of the bit-line read path.
US09424949B2
A shift register circuit includes a first transistor, a capacitor, a pull-up control circuit, a first pull-down circuit, a pull-down control circuit, a second pull-down circuit and a compensation circuit. The compensation circuit further includes a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor. The second transistor, the third transistor, the fourth transistor, and the fifth transistor are corporately used to output a compensation pulse; and the sixth transistor is used to output the compensation pulse to a gate terminal of the first transistor thereby compensating a control signal.
US09424944B2
Apparatuses, systems, methods, and computer program products are disclosed for detecting voltage threshold drift. A method includes programming a predetermined pattern to one page of at least three pages of a set of memory cells. A pattern may have a configuration to reduce a number of bit transitions between abodes of a set of memory cells based on a coding scheme for the set of memory cells. A method includes reading data from a different page of at least three pages. A method includes determining a direction for adjusting a read voltage threshold for a set of memory cells based on read data.
US09424940B1
A nonvolatile memory device includes a substrate, a plurality of memory cells stacked in a direction perpendicular to the substrate, word lines connected to the memory cells, a ground select transistor between the memory cells and the substrate, a ground select transistor between the memory cells and the substrate, a ground select line connected to the ground select transistor, a bit line on the memory cells, and a string select transistor between the memory cells and the bit line. In an erase operation, the ground select line is floated at a time when a specific time passes after the erase voltage is provided to the substrate. And the ground select line is floated at different times depending on a temperature.
US09424934B2
A non-volatile semiconductor memory device utilized to implement the writing of data by adding a predetermined voltage for assigning a word line to a non-volatile memory cell includes a control process or generating and outputting control data implementing a program code for writing data including a word line assignment command and voltage source assignment data, a writing controller decoding the control data and generating a control signal of the word line assignment command and a control signal of the voltage source assignment data, a voltage generation circuit generating several voltages for writing data, and a switch circuit selecting a voltage, corresponding to voltage source assignment data, among several voltages, according to the control signal of the word line assignment command and the control signal of voltage source assignment data and outputting the selected voltage to the word line corresponding to the word line assignment command.
US09424932B2
A programming method is for programming a nonvolatile memory device including a plurality of strings disposed perpendicular to a substrate and connected between bitlines and a common source line. The programming method includes setting up the common source line to a predetermined voltage, floating the setup common source line, performing a program operation on memory cells connected to a selected wordline, and performing a verify operation on the memory cells.
US09424924B2
A non-volatile semiconductor memory device is proposed that has an unprecedented novel structure in which carriers can be injected into a floating gate by applying various voltages of the same polarity. According to the non-volatile semiconductor memory device of the present invention, in a memory transistor, a PN junction is formed at the boundary between a channel region and an opposite polarity type impurity diffusion layer, to allow a floating gate to be charged to have the same polarity as the polarity of the channel region, whereby a part of electrons accelerated in a depletion layer between the channel region and an opposite polarity type extension region, and secondary electrons generated by the accelerated electrons can be injected into the floating gate by being attracted to a gate electrode, as a result of which electrons can be injected into the floating gate even when, without simultaneously applying positive and negative voltages as in the conventional case, various voltages of the same polarity are applied to the floating gate, an impurity diffusion layer, and the opposite polarity type impurity diffusion layer.
US09424921B2
An object is to provide a signal processing circuit which can be manufactured without a complex manufacturing process and suppress power consumption. A storage element includes two logic elements (referred to as a first phase-inversion element and a second phase-inversion element) which invert a phase of an input signal and output the signal, a first selection transistor, and a second selection transistor. In the storage element, two pairs each having a transistor in which a channel is formed in an oxide semiconductor layer and a capacitor (a pair of a first transistor and a first capacitor, and a pair of a second transistor and a second capacitor) are provided. The storage element is used in a storage device such as a register or a cache memory included in a signal processing circuit.
US09424914B2
A resistive memory apparatus and a memory cell thereof are provided. The resistive memory cell includes a first transistor, a second transistor, a first resistor and a second resistor. First and second terminals of the first transistor are respectively coupled to a first bit line and a reference voltage. First and second terminals of the second transistor are respectively coupled to a second bit line and the reference voltage. The first resistor is serially coupled on a coupling path between the first terminal of the first transistor and the first bit line, or on a coupling path between the second terminal of the first transistor and the reference voltage. The second resistor is serially coupled on a coupling path between the first terminal of the second transistor coupled and the second bit line, or on a coupling path between the second terminal of the second transistor and the reference voltage.
US09424905B2
A semiconductor memory device includes a variable resistance memory element connected between first and second conductive lines intersecting each other, and a PN junction diode connected between the variable resistance memory element and the first conductive line. The method of operating the semiconductor device includes supplying the variable resistance memory element with a first directional current flowing from the second conductive line to the first conductive line by applying a first forward bias to the PN junction diode, and supplying the variable resistance memory element with a second directional current flowing from the first conductive line to the second conductive line by applying a reverse bias to the PN junction diode immediately after applying a second forward bias to the PN junction diode.
US09424896B2
Embodiments of a method for operating a computer system are disclosed. In one embodiment, the memory unit has a non-volatile memory array and processing logic and the non-volatile memory array stores initialization data that is used by the processing logic to perform input/output operations of the memory unit. The method involves storing the initialization data in retention registers within the memory unit, wherein the retention registers are separate from the non-volatile memory array and retain data while the memory unit is power gated, using the stored initialization data in the retention registers to initialize the memory unit upon exiting the power gating.
US09424895B2
A semiconductor memory apparatus includes a write driver configured to transfer input data to a data storage region. The semiconductor memory apparatus may also include a sense amplifier configured to sense and amplify the data stored in the data storage region and output output data. Further, the semiconductor memory apparatus may also include an enable signal generation block configured to generate a write driver enable signal and a sense amplifier enable signal according to a comparison result of the input data and the output data.
US09424870B2
Technologies are described herein for preventing adjacent track erasure in a storage device using position error signal compensation from a previously written track in a storage device. A first data track is written to a recording medium in the storage device while position error signal information regarding deviations of a read/write head from an ideal center of the first data track are recorded. The recorded position error signal information is then utilized during the writing of a second, adjacent data track to the recording medium to position the read/write head in order to compensate for non-uniformities in the writing of the first data track.
US09424861B2
The APPARATUSES, METHODS AND SYSTEMS FOR A DIGITAL CONVERSATION MANAGEMENT PLATFORM (“DCM-Platform”) transforms digital dialogue from consumers, client demands and, Internet search inputs via DCM-Platform components into tradable digital assets, and client needs based artificial intelligence campaign plan outputs. In one implementation, The DCM-Platform may capture and examine conversations between individuals and artificial intelligence conversation agents. These agents may be viewed as assets. One can measure the value and performance of these agents by assessing their performance and ability to generate revenue from prolonging conversations and/or ability to effect sales through conversations with individuals.
US09424855B2
An audio device comprises a processor, an audio processing module, a high frequency noise generating circuit, a first switch control circuit, a second switch control circuit, a low pass filter circuit and an adder circuit. The audio device generates a watermark data, an original audio signal and a high frequency noise signal. The high frequency noise signal pass through a first switch control circuit and a second switch control circuit according to watermark data. A low pass filter circuit filters the high frequency noise signal received from the first switch control circuit to form a first add data. An adder circuit receives the first add data from the low pass filter circuit, receives the high frequency noise signal from the second switch control circuit as a second add data, and adds the first add data and the second add data to the original audio signal.
US09424840B1
A speech recognition platform configured to receive an audio signal that includes speech from a user and perform automatic speech recognition (ASR) on the audio signal to identify ASR results. The platform may identify: (i) a domain of a voice command within the speech based on the ASR results and based on context information associated with the speech or the user, and (ii) an intent of the voice command. In response to identifying the intent, the platform may perform a corresponding action, such as streaming audio to the device, setting a reminder for the user, purchasing an item on behalf of the user, making a reservation for the user or launching an application for the user. The speech recognition platform, in combination with the device, may therefore facilitate efficient interactions between the user and a voice-controlled device.
US09424832B1
A system that allows a vehicle operator to record and send a voice message without ever releasing their hands from the wheel and taking their eyes off the road is disclosed. This system also allows incoming notification of messages to be read out loud to the user if they choose. The recipient, if not driving, can choose to see a transcription of the voice message, otherwise the recorded message is played back as recorded by a sending user.
US09424827B2
Electronic percussion instruments with enhanced playing areas and methods and systems for generating electrical signals in response to impacts to a playing surface are disclosed. A semi-permeable playing surface covering an acoustic noise reducing cavity of an electronic percussion instrument may receive an impact within a predefined impact region, and an electrical signal may be generated in response by an electromechanical sensor that senses the impact. In many instances, the generated electrical signal may be configured to be equivalent in magnitude to any other electrical signal generated by the electromechanical sensor, in response to any other received impact within the same predefined impact region.
US09424825B2
A keyboard apparatus has a plurality of white keys and black keys each of which pivot. The keyboard apparatus also has a plurality of reaction force generation members 21w and 21b provided for the white keys and the black keys, respectively. The reaction force generation members 21w and 21b have dome portions 21w1 and 21b1, respectively, which are thin and shaped like a dome so as to be elastically deformed by depression, and base portions 21w3 and 21b3, respectively, which are thick and are formed integrally with the dome portions 21w1 and 21b1 to support the dome portions 21w1 and 21b1, the base portions 21w3 and 21b3 jutting outward from respective lower end surfaces of the dome portions 21w1 and 21b1. The vertical position of the lower end of the dome portion 21w1 is displaced from the vertical position of the lower end of the dome portion 21b1.
US09424815B2
Art stream commands comprising gestures, drawing state, and attribution information are received from one or more clients participating in a collaboration session. The art stream commands enable the rendering of and provide source control for a visual document. Attribution for visual differences may be provided. Each of the one or more clients may rewind and play back the art stream commands to provide a detailed understanding of what was contributed by whom. All changes and image variations are non-destructive.
US09424810B2
System and method for view navigation guidance system for a physical display that is smaller than the virtual display it needs to display. Guidance map placed in a heads-up display layer within a small user defined area of the physical display provides an instantaneous indication of the current position of the screen view with minimal obstruction of the contents information. Color selection for the guidance map is automatically determined based on the background color in the main display layer beneath the map. The guidance map area on a touch screen display may include tapping controls, and the position of the guidance map can be dynamically altered by the user during the view navigation to control the navigation parameters.
US09424809B1
A system for displaying a unified image on a multi-panel display includes a projector and a display engine. The projector is configured to project a patterned projection on a bezel region between an array of display panels arranged to be viewed as a multi-panel display. The display engine is coupled to drive the multi-panel display to display image sections. The patterned projection and the image sections combine to form a unified image.
US09424807B2
A multimedia system includes a main special function register (SFR) configured to store SFR information; a plurality of processing modules each configured to process frames of data, based on the SFR information; and a system control logic configured to control operations of the main SFR and the plurality of processing modules. The plurality of processing modules may process data of different frames at the same time period.
US09424805B2
A display drive integrated circuit includes a frame buffer, an output selector and a timing controller. The output selector selectively outputs one of image data read from the frame buffer and image data transmitted from a source external to the display drive integrated circuit. The timing controller controls output of the image data read from the frame buffer to the display panel in a self-refresh mode, and controls internal display timing to track external display timing when the display drive integrated circuit exits from the self-refresh mode to control the output selector to output the image data transmitted from the source to the display panel when the internal display timing is synchronized to the external display timing.
US09424792B2
A test method for line defect in a display panel (10) comprises: inputting a first ON signal and a first OFF signal into odd rows of gate scanning lines (GE12) and even rows of gate scanning lines (GS13) of the display panel (10) respectively, to turn on transistors controlled by the odd rows of gate scanning lines (GE12), and turn off transistors controlled by the even rows of gate scanning lines (GS13), thereby obtaining a first test image; inputting a second OFF signal and a second ON signal into the odd rows of gate scanning lines (GE12) and even rows of gate scanning lines (GS13) of the display panel (10) respectively, to turn off the transistors controlled by the odd rows of gate scanning lines (GE12), and turn on the transistors controlled by the even rows of gate scanning lines (GE13), thereby obtaining a second test image; comparing the first test image with the second test image to determine that line display defect appearing in the first test image or the second test image are true display defect. Also is disclosed a test device for line defect in a display panel (10). This method allows the test result to approach the lighting test result under module signal input state and can detect true defect of the display panel (10).
US09424790B2
Disclosed are a portable device and a control method thereof for convenient and accurate dimming control. The portable device includes a foldable display unit, a state sensor unit to detect folded and unfolded states of the foldable display unit, an input sensor unit to sense user input and a processor to control the respective units. The processor converts the portable device from a first dimming mode to a second dimming mode upon detection of change of the foldable display unit from the unfolded state to the folded state, perform dimming of the foldable display unit based on a dimming time different with the second dimming time when the user input is sensed in the second dimming mode within a second dimming time, and performs dimming of the foldable display unit after the second dimming time has passed when the user input is not sensed in the second dimming mode within the second dimming time.
US09424784B2
The present invention discloses a local backlight brightness adjustment method for a direct backlight in a display device, the method comprising the steps of: step 1: performing edge detection on an input image to determine whether a sensitive zone exists, the sensitive zone being a portion in the input image in which a gray level difference between adjacent pixels is greater than a predetermined threshold; and Step 2: if a sensitive zone exists, performing a backlight brightness adjustment with respect to a backlight region corresponding to the sensitive zone and a remaining backlight region other than the backlight region corresponding to the sensitive zone, respectively. According to the above-mentioned technical solution, since the backlight brightness adjustment are performed with respect to the backlight region corresponding to the sensitive zone and the remaining backlight region other than the backlight region corresponding to the sensitive zone, respectively, thus, when there is gray level abruptly-varying portion in the image, the display performance of the displayer can still be ensured.
US09424776B2
A pixel driving circuit includes a signal loading component, a storage capacitor, a compensation component, a mirror component, and a drive transistor. In a data transmission stage, the signal loading component transmits a received image data signal to the gate of a drive transistor, which is stored in a storage capacitor; and in a threshold voltage compensation stage, the compensation component connects the gate of the drive transistor to the source of the drive transistor so as to generate a drive signal dependent upon the threshold voltage of the drive transistor from the signal stored in the storage capacitor and to drive an organic light emitting diode to emit light, thus eliminating an influence of the threshold voltage of the drive transistor on the current through the organic light emitting diode and preventing the brightness of the organic light emitting diode from varying over its operating period of time.
US09424773B2
A display panel includes: a display section including a plurality of unit pixels; and a display drive section configured to generate first pixel packets and supply the first pixel packets to the display section, the first pixel packets each including luminance data of a digital signal, the pieces of luminance data determining respective luminances of respective predetermined number of unit pixels of the plurality of unit pixels, and the first pixel packets being equal in number to the predetermined number of unit pixels.
US09424771B2
A unit pixel includes a first sub-pixel that emits a first color light, a second sub-pixel that emits a second color light, a third sub-pixel that emits a third color light, and a fourth sub-pixel that emits a fourth color light. Here, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are arranged in a rhombus structure.
US09424759B2
Disclosed is a Braille display device. The device supports an array of individual Braille cells with corresponding tactile pins. The pins can be selectively lifted by way of reeds to generate Braille characters that can be felt by the user. The Braille characters can correspond to visible characters, such as characters on a computer screen. The display is refreshable to allow for the sequential display of lines, paragraphs, or pages. In accordance with the disclosure, the Braille cells are constructed in a manner that minimizes manufacturing costs and that also permits the size of the display to be greatly reduced.
US09424753B2
A user interface for an integrated autopilot and flight management system for an aircraft includes a plurality of tactical parameter controls for operation of the autopilot and a plurality of strategic parameter controls for operation of the flight management system.
US09424751B2
Systems and methods are disclosed for collecting vehicle data from a vehicle engine computer of a vehicle and a plurality of sensors disposed about the vehicle and generating feedbacks for a driver of the vehicle using at least the vehicle data. The systems and methods additionally provide for receiving user inputs from the driver responding to the feedbacks so that the user inputs are associated with corresponding rule violations that triggered the feedbacks.
US09424749B1
A traffic signal system for congested trafficways has a plurality of stationary alarm light/sensor-reader combinations and mobile alarm light/sensor-reader combinations monitoring each other and monitory tags placed on individuals, machines, and hazards to provide real time alarms to not only pedestrians but also machine operators, who are potentially approaching harm's way, or have the better ability to avert potential harm. Different forms of alarms are provided to indicate different kinds of alarm conditions and to reduce complacency to alarms, and thus improve effectiveness.
US09424748B2
Methods for reporting traffic conditions on road segments containing a bottleneck include: (a) calculating an amount of traffic congestion on a segment of a roadway, the segment containing a bottleneck, based on a free-flow speed specific to a subsection of the segment from which a report of an observed speed is received; and (b) communicating, by the computer processor, information indicative of the amount of traffic congestion on the segment to a client. Apparatuses for reporting traffic conditions on road segments containing a bottleneck are described.
US09424731B2
A multi level hazard detection system for home residents or owners or service providers that want to efficiently monitor and detect numerous common hazards in houses, offices or industrial structures. Hazards that may be dangerous their health or to the structural integrity of their houses, offices and industrial structures and all appliances and systems that are of these structures such as heating and cooling systems, pipes and more. By detecting hazards in advance, residents home owners and service providers can better protect their property. The multi level hazard detection system generally includes Single or Multi Sensor Device (170) that can be based on Low Power Communication Module (110), A Monitor and Control Device (140) which can be a mobile phone, desktop or laptop computer, an Analytic Server (150) and Relay Dongle (160).
US09424729B2
A mobile tracking unit includes a controller having a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions are executable by the processor to communicate with a control unit of an automation and security system, determine a position of the mobile tracking unit relative to a base station using a low power location module, and communicate the position of the mobile tracking unit to at least one of the base station and a control unit of the automation and security system. When the mobile tracking unit is outside a specified range from the mobile tracking unit, the controller continues tracking the position of the mobile tracking unit with the low power location module. When the mobile tracking unit is inside the specified range, the controller determines the position of the mobile tracking unit using a high power location module.
US09424728B2
The instant disclosure provides a child safety seat alarm to notify the driver of a vehicle that an infant is in its carrier inside of the vehicle when a personal electronic device carried by the driver is moved a great distance from the carrier. The instant disclosure provides a computer application for notification of user selected contacts via SMS messaging, e-mail messaging, or social media alerts.
US09424723B2
A luggage bag is disclosed which comprises electronic circuits comprising a geolocation module and a communication module that are designed such that an information item relating to the position of the luggage bag may be remotely accessible to a user, the communication module exhibiting a switch-off device allowing its deactivation by the user independently of the remainder of the electronic circuits. The electronic circuits comprise a detection module, designed to take measurements of at least one physical quantity and to identify conditions corresponding to the landing of an aircraft. They can also be programmed to operate in an aircraft mode in which, after deactivation of the communication module in response to an action of the user, the detection module performs measurements staggered over time, the electronic circuits being designed to automatically reactivate the communication module subsequent to the identification of conditions corresponding to the landing of an aircraft.
US09424707B2
An actuated castellation plate can be arranged across a length of a currency passageway of a currency acceptor assembly and configured in an open state. Pressure from an attempted string fraud, such as pulling in reverse a bill across the castellation plate, can actuate the castellation plate to a closed state, obstructing the currency passageway so that the bait bill cannot be retrieved. Embodiments can include a currency acceptor including a currency passageway, mounting assembly, currency storage assembly having an entrance, the currency passageway being arranged to guide a currency denomination to the entrance of the currency storage assembly, and an actuated castellation plate including an array of teeth coupled to a baseplate including a receptacle and two opposing mounting ends, the castellation plate being configured at the entrance of the cashbox assembly to transfer between an open and closed state. Related apparatus, systems, techniques, and articles are also described.
US09424690B2
A method, comprising: obtaining an image data of a physical object; the physical object comprises a plurality of markers positioned on the outer surface of the physical object; analyzing, using a computer, the data, to identify visual markers information indicative of at least some of a plurality of markers; determining an orientation and a location of the physical object in response to predefined attributes of the plurality of markers and to the visual markers information.
US09424689B2
An augmented reality technique is implemented by, for example, an information processing apparatus which is configured to function and operate as an image acquiring unit that acquires an image of a real space captured by an imaging device, a feature detection unit that detects one or more features from the captured image, an image generating unit that generates an image of a virtual space and places a virtual object made to correspond to the detected feature at a position in the virtual space based on the position of the detected feature in the acquired real space image, and a display control unit that causes an image to be displayed on a display device such that a user sees the virtual space image superimposed upon the acquired real space image. In one example operation implementation, when a first feature and a second feature are detected together in a captured real space image, the image generating unit determines a first virtual object corresponding to a combination of the first feature and the second feature and places the first virtual object at a position in the virtual space based on a position of the second feature in the acquired real space image.
US09424683B2
A transposing apparatus is configured by a computer controlling a computing device having computing elements arranged into a matrix and memory devices connected to the computing elements. The computing device executes an electromagnetic field analysis process on latticed three-dimensional analysis subject data present in a three-dimensional coordinate system. The computer is configured to detect the number of lined-up lattices in a direction of a first axis, in a direction of a second axis, and in a direction of a third axis of the coordinate system, through detection on the three-dimensional analysis subject data; transpose a group of lattices of the three-dimensional analysis subject data, based on the detected numbers of lined-up lattices and on the number of lined-up computing elements in a row direction and in a column direction; and output to the computing device, the three-dimensional analysis subject data transposed.
US09424671B1
Implementations generally relate to optimizing a photo album layout. In some implementations, a method includes receiving a plurality of images and determining a target arrangement. The method also includes arranging the plurality of images in an N-dimensional arrangement based on a predetermined distance function. The method also includes arranging the plurality of images in the target arrangement based on the N-dimensional arrangement.
US09424669B1
A system comprising a computer-readable storage medium storing at least one program and a method for generating graphical representations of event participation flows are presented. In example embodiments, the method includes receiving a subject event identifier entered as user input via a user interface. The method further includes accessing event data including a plurality of event data records that include an event record corresponding to the subject event identifier. The event record includes a set of participant identifiers corresponding to participants of a subject event identified by the subject event identifier. The method further includes determining an event participation flow for the participants of the subject event using the event data, and causing presentation of a graphical representation of the event participation flow in the user interface.
US09424668B1
Systems and methods are provided for sharing a screen from a mobile device. For example, a method includes receiving an image from a mobile device, performing recognition on the image to identify space-delimited strings, and generating a content graph for the image, the content graph having content nodes that represent at least some of the strings and the content graph having edges that represent a relative position of strings associated with the content nodes connected by the edges. The method may also include repeating the receiving, performing recognition, and generating for a plurality of images, the plurality of images belonging to a session, and generating a combined graph from the plurality of content graphs based on similarity of content nodes between content graphs, the combined graph representing text from the plurality of images in reading order.
US09424657B2
An image processing method for detecting an image motion information between a first image unit and a second image unit is provided. The first image unit and second image unit respectively comprise a plurality of blocks, and each of the blocks comprises a plurality of pixels. The image motion detection method comprises: analyzing pixels at the same position in all blocks of the first image unit to generate a first image statistical information; analyzing pixels at the same position in all blocks of the first image unit to generate a first image statistical information; and comparing the first image statistical information with the second image statistical information to determine the image motion information.
US09424655B2
An image processing apparatus includes an acquisition unit configured to acquire a video, a superimposition unit configured to superimpose an image onto the video acquired by the acquisition unit, and a detection unit configured to detect the emergence of an object in a video in a detection area set on the video acquired by the acquisition unit, wherein the superimposition unit superimposes an image corresponding to the size of the object to be detected when emerging by the detection unit onto the video in the detection area, and outputs the resultant video to the detection unit.
US09424654B1
Analog circuits for detecting edges in pixel arrays are disclosed. A comparator may be configured to receive an all pass signal and a low pass signal for a pixel intensity in an array of pixels. A latch may be configured to receive a counter signal and a latching signal from the comparator. The comparator may be configured to send the latching signal to the latch when the all pass signal is below the low pass signal minus an offset. The latch may be configured to hold a last negative edge location when the latching signal is received from the comparator.
US09424653B2
A computer implemented method for generating a representative thumbnail for an image. The method comprises determining a representative area of an image, the determining comprising determining an absence of faces in the image; dividing the image into one or more zones; and selecting a zone with maximum edge strength as the representative area; and generating a thumbnail by cropping the image to the representative area.
US09424646B2
A control system executes a first control operation, and then executes a second control operation. In the first control operation, the image processing section obtains the image data and specifies a position of a characteristic part. The control section determines a control instruction for accelerating an object to a predetermined first speed based on the specified position of the characteristic part and then decelerating the object to a predetermined second speed lower than the first speed, to move the object to an intermediate target position away from the final target position by a predetermined margin distance. In the second control operation, the image processing section obtains the image data during movement of the moving mechanism and specifies the position of the characteristic part, and the control section determines a control instruction for positioning the object to the final target position based on the specified position of the characteristic part.
US09424635B2
Individual grain sorting of objects from bulk materials (3) on a conveying device (1) and an actuable discharge unit (2) which separates into fractions, the height distribution of the object (3.1) and the propagation of a light source (4) are advantageously used as sorting criterion, wherein a light-band (4.1) is projected transversely with respect to a conveying direction of the bulk material (3) on a plane of the conveying device (1), the objects (3.1) are moved through under the light-band (4.1), a first part (4.1.1) of the light is reflected, a second part (4.1.2) enters again at an entry point (11.1), is scattered and exits again at an exit point (3.1.2), a scattered propagation (B) is detected by a camera (9), and contiguous regions are identified in buffered rows (13), and the measured values are subjected to an evaluation and are combined to form characteristic values, and the discharge unit (2) is actuated in dependence on preset sorting parameters.
US09424633B2
Provided is an image processing apparatus including an acquisition section that acquires an object image which is an editing object, a feature quantity acquisition section that acquires a feature quantity of a reference image which is referred to when the object image is edited, a feature-reflected image generation section that reflects a feature of the reference image on the object image by using the feature quantity acquired by the feature quantity acquisition section, and generates a feature-reflected image which is the object image on which the feature is reflected, and a reflection degree changing section that changes a degree of reflection of the feature in the feature-reflected image by using an adjustment value which is input by a user.
US09424624B2
Systems and methods for upscaling graphics resolution are provided. The systems and methods may selectively upscale graphics frames having a first resolution to a second resolution by various scaling methods. Depending on a variety of factors, at least a first mode of upscaling and a second mode of upscaling may provide for improved upscaling on a variety of graphics data.
US09424623B2
An image processor includes: a first division control information acquiring circuit configured to acquire division control information of a first chip; a second division control information acquiring circuit configured to acquire division control information of a second chip; a division process control circuit configured to determine a ratio at which a process is performed by the first image processing circuit and a ratio at which a process is performed by the second image processing circuit, based on the division control information of the first chip and the division control information of the second chip; a division circuit configured to divide data to be subjected to image processing into first-chip data and second-chip data at the determined ratios; the first image processing circuit configured to perform image processing on the first-chip data; and the second image processing circuit configured to perform image processing on the second-chip data.
US09424622B2
Methods and apparatus for providing multiple graphics processing capacity, while utilizing unused integrated graphics processing circuitry on a bridge circuit along with an external or discrete graphics processing unit is disclosed. In particular, a bridge circuit includes an integrated graphics processing circuit configured to process graphics jobs. The bridge circuit also includes an interface operable according to interface with a discrete graphics processing circuit. A controller is included with the bridge circuit and responsive whenever the discrete graphics processing circuit is coupled to the interface to cause the integrated graphics processing circuit to process a task of the graphics job in conjunction with operation of the discrete graphics processing circuit that is operable to process another task of the graphics job. Corresponding methods are also disclosed.
US09424621B2
This invention relates to a method of processing a plurality of graphical programs on a centralized computer system whereby the images produced by the programs are compressed and transmitted to remote processing devices where they are decompressed. Compression assistance data (CAD) is produced by inspecting instructions outputted by the programs and the CAD is then used in the compression step.
US09424620B2
A method performed by a processor is described. The method may include identifying a graphics processing unit (GPU) phase of a frame, using said identified GPU phase to obtain frequency scalability information for said identified GPU phase, and determining whether to change a frequency at which a GPU is to draw said frame within said phase based on said frequency scalability information.
US09424615B2
A system and method are disclosed for determining and recommending a coaching decision during a football game, where the recommended coaching decision corresponds with the highest probability of winning the football game.
US09424606B2
An enhanced claims settlement apparatus may process insurance claims rapidly and accurately. The apparatus may first receive a notification of loss associated with an insured item (e.g., car, boat, truck, home, etc.). The apparatus may then apply various algorithms for using sensors to identify, analyze, and estimate the cost of damage associated with the insured item. The sensors that are a part of the enhanced claims settlement server may include cameras, tactile sensors, electromagnetic sensors, etc. that may communicate data to a processor associated with the server. Once the data has been generated and analyzed by the sensors, a claim settlement file may be transmitted to a claimant.
US09424604B2
Data streams are generally selected according to user preferences and transmitted to the user in general alignment with expressed preferences of the user. Such data streams may be music, including music videos. Users may indicate their general or specific preferences with regards to song, artists, or albums. Any other aspects or factors that might affect the user's preferences can be taken into account. A playlist is created that combines all of these factors. The playlist then serves as the basis for feeding the data streams to the user. Each user is able to express his or her own preferences and receive music corresponding to those preferences on an on-going basis.
US09424597B2
In an example embodiment, text is received at an ecommerce service from a first user, the text in a first language and pertaining to a first listing on the ecommerce service. Contextual information about the first listing may be retrieved. The text may be translated to a second language. Then, a plurality of text objects, in the second language, similar to the translated text may be located in a database, each of the text objects corresponding to a listing. Then, the plurality of text objects similar to the translated text may be ranked based on a comparison of the contextual information about the first listing and contextual information stored in the database for the listings corresponding to the plurality of text objects similar to the translated text. At least one of the ranked plurality of text objects may then be translated to the first language.
US09424590B2
A method and a system for real time targeted advertising using purchase transaction data and payment card holder activity and location information in a retail environment. The system includes a radio frequency identification (RFID) reader situated in a retail environment. The RFID reader communicates with an RFID tag that is situated on a payment card of a payment card holder to track the payment card holder as the payment card holder walks around in the retail environment. The system also includes a processor configured to select a predictive behavioral model based on payment activities attributable to the payment card holder and payment card holder activity and location in a retail environment, associate the predictive behavioral model with merchant advertising information, and convey the associated information to a merchant to enable the merchant to make a targeted offer to the payment card holder.
US09424587B2
System and method for facilitating advertisements within viewed content. The advertisements may be banner advertisements or other advertisement. The advertisements may be included in such a manner that if a user skips or otherwise fast forwards through the advertisements, the user if force to skip through at least a portion of the viewed content.
US09424586B1
Technologies are described herein for remote management of sensors and other functionalities in a digital signage device through a remote management server. In particular, a Digital Signage Control System (“DSCS”) facilitates delivery of sensor command parameters to particular signage devices or a network of signage devices as specified in a Sensor Command Deployment Plan. After receiving various sensor commands from a user at a user interface, a Sensor Command Deployment Module generates a Sensor Command Deployment Plan (“SCDP”), which specifies which sensors or controls should be adjusted on signage device(s) and when the adjustments should be made. Subsequently, a Signage Communication Module (“SCM”) waits for a request for sensor instructions from a signage device specified in the plan. Once the request is received, the SCM deploys specific instructions or commands (parameters) to a particular signage device wherein the command is executed at the signage device.
US09424582B2
A system and method for managing customer address information in electronic commerce using the Internet are provided. Customers' detailed address information is received from customer terminals connected over the Internet, a unique address number corresponding to the detailed address information is produced, and the produced unique address number and the corresponding detailed address information are separately stored and managed in separate database (DBs), thereby effectively preventing leakage of the customers' detailed address information due to hacking or a malicious program.
US09424578B2
Systems and methods for providing gesture functionality are provided. In example embodiments, a gesture input is received. The gesture input represents a commerce-related action, whereby the commerce-related action relates to an action to be performed within a networked environment. A determination is performed to determine that the commerce-related action is executable. The commerce-related action is then performed based on the determination that the commerce-related action is executable.
US09424574B2
Embodiments of the present invention disclose a financial institution system maintained by a financial institution and for tokenization of user accounts for using a direct payment authorization channel, whereby a third party payment authorization network is avoided. Embodiments establish a direct channel of communication between the system and a merchant or a merchant network in communication with the merchant; wherein the direct channel of communication comprises a network communication channel without a third party payment authorization system; receive a token issued by the financial institution and associated with a user account associated with a customer of the financial institution; receive transaction data comprising an amount associated with a transaction between the customer of the financial institution and the merchant; and determine whether to authorize the transaction based on the received token and the received transaction data.
US09424556B2
Techniques for linking multiple contact identifiers of an individual include receiving first data that indicates contacts of a first user at first services. Contact identifiers for a different second user at second services are determined based at least in part on the contacts. Second data that indicates an association among the second user and the candidate contact identifiers is sent to the first user. In some embodiments on a client, techniques include determining to send first data that indicates contacts of a first user at first services; and receiving second data. The second data indicates an association among a different second user and candidate contact identifiers for the second user at second services based at least in part on the contacts. A prompt is presented for the first user to approve an association between the second user and a candidate contact identifier.
US09424548B1
Disclosed are various embodiments for translation of destination identifiers. In one embodiment, an input including a destination identifier is received. For example, the destination identifier may be affixed to the exterior of a shipment and scanned. The destination identifier is translated into a geographic address based at least in part on a stored mapping. The geographic address is then rendered in a user interface.
US09424547B2
Methods of causing transport of one or more items between two or more locations using computerized apparatus. In one embodiment, the one or more items comprise one or more pieces of luggage of a user which are shipped from a transportation facility such as an airport via user-instigated actions at a kiosk located within the facility. In one variant, user information is provided to the kiosk via a personal electronic device of the user (e.g., provided wirelessly via a smartphone), and the kiosk accesses a travel reservation system to obtain information about the routing of the luggage.
US09424543B2
A method to authenticate an identity of a responder. The method includes receiving a request and determining, by one or more computer processors, a reviewer for the request. A custom key is generated for the reviewer and the request, and at least one URL is generated that contains the custom key. At least one URL is sent, along with the request, to the reviewer. Upon receiving a response to the request that includes a selection of one URL, it is determined whether the response was received from the determined reviewer for the request.
US09424538B1
A security aware email server and a method of managing incoming email are described. The server includes a memory device configured to store rules, instructions, and user preferences. The processor makes a determination of whether a sender of an incoming email used a secure or unsecure sending network to send the email and determines an action to take with the email based on the determination and the user preferences.
US09424536B2
A system and method for facilitating integrating enterprise data from multiple sources for display via in a common interface. An example method includes displaying, via a first user interface display screen, a first set of one or more personnel icons representative of one or more enterprise personnel, and providing a first user option to select one or more of the personnel icons. A second user interface display screen may be displayed in response to or after selection of one or more of the personnel icons. The second user interface display screen presents a first type of data. The second user interface display screen further provides a second user option to select one or more user interface features associated with the first type of data, and to then trigger display of a third user interface display screen. The third user interface display presents a second type of data that is associated with the first type of data.
US09424534B2
An apparatus includes a database of content and a content system. The database stores content related to a set of entities to be voted upon in a voting system, wherein there is at least one piece of content for each selection. The content system receives a vote of a user from the voting system and at least an identifier of a cellphone of the user and provides content related to the vote from the database to the cellphone. At least a portion of the content is playable on the cellphone.
US09424519B1
A diagnostic monitoring system and method is employed for one or more vapor compression systems such as air conditioners and heat pumps having a compressor, an indoor air handler fan coil and an outdoor condensor. Temperature, voltage and current sensors are provided at the outdoor condensor to determine that at least one vapor compression system is operating properly. Data obtained from the sensors is wirelessly transmitted to a receiving-device for use by the systems' custodian or repair service provider and includes information concerning an occurrence of periods when one or more of the vapor compression systems are operating at an abnormal state.
US09424518B1
A method of determining a set of prescribed actions includes receiving a configuration script identifying a set of influencers, a set of performance indicators, a model type, a target time, and a prescription method. The method further includes deriving a model of the model type based on data associated with the set of influencers or with the set of performance indicators. The method also includes projecting a set of future influencer values associated with the set of influencers and projecting a set of future indicator values of the set of performance indicators at the target time using the model. The method can further include prescribing using the prescription method and based on projecting using the model a set of prescribed actions associated with the subset of actionable influencers. The method also includes displaying the set of prescribed actions.
US09424517B2
A method of assessing chemical products includes: receiving input data including identification of a chemical substance at a processing device; evaluating a regulatory impact of the chemical substance based on at least one of global regulation data, regional regulation data and jurisdiction-specific regulation data, and outputting a regulatory impact assessment; evaluating potential hazards posed by the chemical substance based on available data related to characteristics of the chemical substance by comparing the characteristics to a plurality of criteria including environmental criteria, toxicity criteria related to effects on human health, and physical criteria related to hazards encountered during material transportation and handling, and outputting a chemical hazard assessment; and generating a chemical assessment report indicating potential impact due to use of the chemical substance, the chemical assessment report indicating chemical assessment results that include the regulatory impact assessment and the chemical hazard assessment.
US09424512B2
A hierarchy of computing modules is configured to learn a cause of input data sensed over space and time, and is further configured to determine a cause of novel sensed input data dependent on the learned cause. At least one of the computing modules has a sequence learner module configured to associate sequences of input data received by the computing module to a set of causes previously learned in the hierarchy.
US09424507B2
Dual-interface Integrated Circuit (IC) card components and methods for manufacturing the dual-interface IC card components are described. In an embodiment, a dual-interface IC card component includes a single-sided contact base structure, which includes a substrate with an electrical contact layer. On the single-sided contact base structure, one or more antenna contact leads are attached to the single-sided contact base structure to form a dual-interface contact structure, which is a component of a dual-interface IC card. Other embodiments are also described.
US09424505B2
A luminescent nanocomposite comprising functionalized graphene and a luminescent moiety, its fabrication, and uses are described. The luminescent moiety is anchored non-covalently to the functionalized graphene. Luminescence properties of the nanocomposite may be modulated by choosing appropriate luminescent moieties such as native lactoferrin, native lactoferrin protected gold clusters, and so forth. Mechanical properties of the nanocomposite may be modulated by adding a biopolymer such as Chitosan. The nanocomposite may be used as a luminescent ink for encoding information, or a luminescent film for tagging articles of manufacture such as electronic waste components.
US09424499B2
A method is provided for enhancing a grayscale raster image comprising pixels. The method comprises the steps of composing a second raster image of equal dimensions to said raster image, selecting a target pixel in the second raster image, having a target position, and deriving a grayscale value for the target pixel from a grayscale value of a pixel in said raster image that is in a neighborhood of a pixel on a position corresponding to the target position, thereby dispersing the gray value of a pixel in a predetermined range around its original position and working the second raster image up for a halftoning process without using pixel segmentation.
US09424496B2
An image forming apparatus for easily setting a parameter for avoiding an occurrence of defective image by the sector deformation is provided. The image forming apparatus forms a test image. The test image having a first line drawing and a second line drawing, each of which is extending in a first direction, and the first line drawing and the second line drawing are provided at different positions in a second direction which is perpendicular to the first direction. Further, the image forming apparatus obtains the length information of the first and the second line drawings. Based on the length information of the first and the second line drawings, a correction condition is set. Then, the image forming apparatus corrects the image data based on the correction condition according to a position of the second direction.
US09424494B1
An approach is provided in which a knowledge manager processes an image using a convolutional neural network. The knowledge manager generates a pixel-level heat map of the image that includes multiple decision points corresponding to multiple pixels of the image. The knowledge manager analyzes the pixel-level heat map and detects sets of decision points that correspond to target objects. In turn, the knowledge manager marks regions of the heat map corresponding to the detected sets of per-pixel decision points, each of the regions indicating a location of the target objects.
US09424482B2
A method and apparatus for image processing to avoid counting shelf edge promotional labels when counting product labels. Shelf edges are identified by detecting shelf edge content in a captured image by comparing the image to reference images of shelf edge content. Detected occurrences of shelf edge content are demarcated using a geometric pattern having corners at coordinates corresponding to positions around the identified shelf edge content. Corresponding corners are grouped into clusters, and the clusters are analyzed to define the upper and lower bounds of a shelf region in the image.
US09424481B2
Methods, systems, and computer-readable mediums are presented that process and store images efficiently in a memory system. When a new image is received, it is compared to a plurality of reference images. The most similar reference image is located, and a delta image is generated representing a difference between the reference image and the new image. Instead of storing the entirety of the new image, the delta image can be stored along with a reference to the corresponding reference image, such that the new image can be restored from the delta image and the reference image. The total number of reference images and delta images can be dynamically balanced such that predetermined ratios of image numbers or image sizes can be maintained.
US09424478B2
Multimodal biometric profiling may include receiving a cover image and a biometric template for a person. An indication of a security requirement related to biometric profiling for the person may be received. A threshold value may be determined based on the indicated security requirement. The threshold value may be used to limit a number of biometric template bits of the biometric template that are embedded in a predetermined bit position of a cover image pixel of the cover image based on cover image intensity associated with the predetermined bit position.
US09424476B2
A method for detecting a vehicle sunvisor's state includes obtaining a detected image; conducting a gray-scale preprocessing on the detected image, to obtain a gray-level image; conducting a main connected region extraction on the gray-level image, and calculating a geometric feature and a rectangle similarity of each main connected region; conducting a horizontal long edge extraction on the gray-level image, and conducting feature matching operation between horizontal long edges and main connected regions to obtain a region edge matching relationship; determining the sunvisor's state based on the region edge matching relationship, the geometric feature of main connected regions and rectangle similarity of main connected regions. The present invention can be widely applied in the field of image process.
US09424470B1
An example method includes receiving a plurality of templates of a plurality of objects, where a template comprises feature values sampled at corresponding points of a two-dimensional grid of points positioned over a particular view of an object and scaled based on a depth of the object at the particular view. The method may further include receiving an image of an environment and determining a matrix representative of the image, where a row of the matrix comprises feature values sampled at a particular point of the two-dimensional grid positioned over one or more locations within the image and scaled based on depths of the one or more locations. The method may additionally include determining at least one similarity vector corresponding to at least one template and using the at least one similarity vector to identify at least one matching template for at least one object located within the image.
US09424468B2
A position, behavior state and movement state of a moving object are detected, together with plural categories of track segment region and stationary object regions, using an environment detection section. A presence probability is applied to the detected track segment regions and stationary object regions and a presence probability map is generated, using a map generation section. A moving object position distribution and movement state distribution are generated by a moving object generation section based on the detected moving object position, behavior state and movement state, and recorded on the presence probability map. The moving object position distribution is moved by a position update section based on the moving object movement state distribution. The moved position distribution is changed by a distribution change section based on the presence probabilities of the presence probability map, and a future position distribution of the moving object is predicted on the presence probability map. Consequently, the future position of the moving object can be predicted with good precision under various conditions.
US09424465B2
A method for identifying sections of contracts. This method works well with documents that originated from scanned images, i.e., documents that could possibly include noise and misleading cues.
US09424463B2
A system for image manipulation enables an improved video conferencing experience. The system includes a camera; a display screen adjacent to the camera; a processor coupled to the camera and the display screen; and a memory coupled to the processor. Instructions executable by the processor enable receiving a source image from the camera and generating a synthetic image based upon the source image. The synthetic image corresponds to a view of a virtual camera located at the display screen.
US09424454B2
An apparatus for use in decoding a bar code symbol may include an image sensor integrated circuit having a plurality of pixels, timing and control circuitry for controlling an image sensor, gain circuitry for controlling gain, and analog to digital conversion circuitry for conversion of an analog signal to a digital signal. The apparatus may also include a PCB for mounting the image sensor integrated circuit and light source bank. The connection between the image sensor integrated circuit and/or light source bank and the PCB characterized by a plurality of wires connecting a plurality of bond pads and a plurality of contact pads, where the wires, bond pads, and contact pads provide electrical input/output and mechanical connections between the image sensor integrated circuit and the PCB. The apparatus may be operative for processing image signals generated by the image sensor integrated circuit for attempting to decode the bar code symbol.
US09424451B2
A low-energy transceiver tag is described, as well as methods of using the low-energy transceiver tag to enable secure communication with a vehicle. The low-energy transceiver tag includes a substrate, and electronic circuitry carried by the substrate having a transceiver circuit coupled to a power circuit. The transceiver circuit may be configured to transmit a preconfigured answer signal in response to receiving a query signal. In addition, the preconfigured answer signal may be a low-energy response associated with a remotely-located trust anchor.
US09424448B2
A locating device for determining a distance of an RFID tag with respect to an interface between two media comprising an inductive coupling antenna and a sensor for determining a distance between the antenna and the interface. There is an energizing circuit configured to energize the antenna to generate an electromagnetic field with various successive amplitude values and a detection device for detecting an electromagnetic field response from the RFID tag. There is a processing circuit configured to determine several pairs of information, each pair including: a distance between the antenna and the interface and a minimum electromagnetic field value detected by the detection device from the RFID tag at the determined distance between the antenna and the interface. The processing circuit also evaluates the distance between the RFID tag and the interface as a function of the several pairs.
US09424441B2
Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.
US09424439B2
Techniques for secure data synchronization are described. In one or more implementations, techniques may be employed to conserve high cost data storage by storing larger portions of encrypted data in low cost storage, while storing relatively smaller encryption keys in higher cost storage. A device that is granted access to the encryption keys can retrieve the encrypted data from the low cost storage and use the encryption keys to decrypt the encrypted data.
US09424434B2
Data theft prevention technology for a personal electronic device is provided. When an internet-communication address of the personal electronic device is detected by a server through the internet and the server determines that the detected internet-communication address has been listed in a lost list, a processing unit of the personal electronic device operates in accordance with anti-theft software to execute the codes contained in a BIOS memory of the personal electronic device to set a medium password for a user-data storage medium of the personal electronic device and to prohibit the use of the personal electronic device.
US09424432B2
An information processing system provisions a client account for a user to enable a client computer associated with the user to store information in an elastic storage system and to prohibit the client computer, the information processing system, and the elastic storage system from altering and from deleting the stored information during an authorized retention period. Data messages are received from one or more client computers and include information that is required to be stored for the authorized retention period. That information is transmitted via one or more data communications networks to the elastic storage system for storage so that the stored information is non-rewriteable and non-erasable during the authorized retention period. The secure data center receives the retrieved copy and provides it to the user device. The elastic storage system permits deletion, modification, or destruction of the stored information only when a trusted independent third party having predetermined authentication information associated with the client account provides the predetermined authentication information to the elastic storage system.