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发明授权
US09425273B2 Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the same 有权
包括具有至少五个具有特定空间和电气关系的栅极级导电结构的集成电路的半导体芯片及其制造方法

Semiconductor chip including integrated circuit including at least five gate level conductive structures having particular spatial and electrical relationship and method for manufacturing the same
摘要：
A semiconductor chip region includes a first conductive structure (CS) that forms a gate electrode (GE) of a first transistor of a first transistor type (TT) and a GE of a first transistor of a second TT, a second CS that forms a GE of a second transistor of the first TT, a third CS that forms a GE of a second transistor of the second TT, a fourth CS that forms a GE of a third transistor of the first TT, and a fifth CS that forms a GE of a third transistor of the second TT. Diffusion terminals of the first and second transistors of the first TT are electrically connected. Diffusion terminals of the first and second transistors of the second TT are electrically connected. Diffusion terminals of the second and third transistors of both the first TT and second TT are electrically connected.
摘要（中）：

半导体芯片区域包括形成第一晶体管类型（TT）的第一晶体管的栅电极（GE）和第二TT的第一晶体管的GE的第一导电结构（CS），形成第二晶体管的第二晶体管的GE GE的第一TT的第二晶体管，形成第二TT的第二晶体管的GE的第三CS，形成第一TT的第三晶体管的GE的第四CS，以及形成第一TT的第五CS 第二TT的第三晶体管。 第一TT的第一和第二晶体管的扩散端子电连接。 第二TT的第一和第二晶体管的扩散端电气连接。 第一TT和第二TT的第二和第三晶体管的扩散端电连接。

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