Method for validating a software
    1.
    发明授权

    公开(公告)号:US12026081B2

    公开(公告)日:2024-07-02

    申请号:US17147141

    申请日:2021-01-12

    申请人: Robert Bosch GmbH

    摘要: A method for validating a software, particularly a driver-assistance software. The method includes receiving of a sensor signal that is to be processed by the software; determining of a reference signal by an adaptive filter based on the sensor signal, the reference signal representing an anticipated sensor signal; determining an error signal based on the sensor signal and the reference signal, the error signal representing a performance of the software; determining an anti-sensor signal by a machine-learning unit based on the sensor signal, the machine-learning unit being trained with sensor signals already evaluated; controlling of the adaptive filter by a control unit based on the determined error signal and the adaptive anti-sensor signal; and validation of the software based on the determined error signal.

    Near-zero latency analog bi-quad infinite impulse response filter

    公开(公告)号:US11689393B1

    公开(公告)日:2023-06-27

    申请号:US17586668

    申请日:2022-01-27

    IPC分类号: H04L25/03 H03H21/00 H04L25/02

    摘要: Examples provide a method and apparatus for an analog bi-quad infinite impulse response (IIR) filter. An amplifier generates a positive output signal corresponding to a received RF signal and a negative output signal. A set of selectively switchable time-delay circuits associated with a positive arm of the filter causes a predetermined delay corresponding to a desired sample frequency. A first set of configurable variable gain amplifiers amplify the positive output signal to establish a set of positive coefficients. A set of selectively switchable time-delay circuits associated with a negative arm of the filter causes a predetermined delay. A delayed negative output signal is generated which is amplified by a second set of configurable variable gain amplifiers to establish a set of negative coefficients. A set of power combiners function as sum junctions to combine the delayed positive output signals and the delayed negative output signals into a single output signal.

    Systems and methods for high performance filtering techniques for sensorless direct position and speed estimation

    公开(公告)号:US11671042B2

    公开(公告)日:2023-06-06

    申请号:US17484313

    申请日:2021-09-24

    发明人: Matthias Preindl

    IPC分类号: H02P21/13 H02P21/18 H03H21/00

    摘要: Disclosed are implementations, including a method that includes obtaining measurement samples relating to electrical operation of an electric motor drive providing power to an electric motor, deriving, based on the samples, instantaneous estimates for parameters characterizing speed and/or position of the motor according to an optimization process based on a cost function defined for the samples, and applying a filtering operation to the instantaneous estimates to generate filtered values of the motor's speed and/or position. The filtering operation includes computing the filtered values using the derived instantaneous estimates in response to a determination that a computed convexity of the cost function is greater than or equal to a convexity threshold value, and/or applying a least-squares filtering operation to the derived instantaneous estimates and using at least one set of previous estimates derived according to the optimization process applied to previous measurement samples.

    Digital noise-shaping FFE/DFE for ADC-based wireline links

    公开(公告)号:US11522735B1

    公开(公告)日:2022-12-06

    申请号:US16998864

    申请日:2020-08-20

    申请人: Xilinx, Inc.

    IPC分类号: H04L25/03 H03H21/00

    摘要: Apparatus and associated methods relate to an ADC-based digital receiver including a feedforward equalizer (FFE) that has m precursor taps and n postcursor taps to equalize the precursor portion, and to adapt postcursor intersymbol interference (ISI) through a predetermined equalization coefficient selected to counteract the noise boosting effect associated with the precursor equalization. In an illustrative example, the receiver may dynamically balance noise and ISI through adaptively determining a coefficient hp1 of a first postcursor tap of a first FFE and a coefficient h1 of a first postcursor tap of a second equalizer adapted to substantially reduce or eliminate additional ISI introduced by the first FFE. The first FFE may optimize ISI removal and noise reduction, for example. One of the coefficients h1 and hp1 may be predetermined, and then the other coefficient may be iteratively adapted to trade off precursor ISI and postcursor ISI to minimize BER.

    Adaptive volterra compensator
    5.
    发明授权

    公开(公告)号:US11463072B1

    公开(公告)日:2022-10-04

    申请号:US15807419

    申请日:2017-11-08

    摘要: The present invention is a computationally-efficient compensator for removing nonlinear distortion. The compensator operates in a digital post-compensation configuration for linearization of devices or systems such as analog-to-digital converters and RF receiver electronics. The compensator also operates in a digital pre-compensation configuration for linearization of devices or systems such as digital-to-analog converters, RF power amplifiers, and RF transmitter electronics. The adaptive Volterra compensator effectively removes nonlinear distortion in these systems by implementing an adaptive background algorithm to periodically update actual filter coefficients to maintain optimal performance in operating conditions varying over time (e.g., temperature, frequency, signal level, and drift); or both. The xadaptive background algorithm calculates the optimal nonlinear filter coefficients to reduce nonlinear distortion.

    Precision digital to analog conversion in the presence of variable and uncertain fractional bit contributions

    公开(公告)号:US11368163B2

    公开(公告)日:2022-06-21

    申请号:US17162635

    申请日:2021-01-29

    发明人: Gideon Van Zyl

    摘要: This disclosure describes systems, methods, and apparatus for a digital-to-analog (DAC) converter, that can be part of a variable capacitor and/or a match network. The DAC can include a digital input, an analog output, N contributors (e.g., switched capacitors), and an interconnect topology connecting the N contributors, generating a sum of their contributions (e.g., sum of capacitances), and providing the sum to the analog output. The N contributors can form a sub-binary sequence when their contributions to the sum are ordered by average contribution. Also, the gap size between a maximum contribution of one contributor, and a minimum contribution of a subsequent contributor, is less than D, where D is less than or equal to two time a maximum contribution of the first or smallest of the N contributors.

    Systems and methods for high performance filtering techniques for sensorless direct position and speed estimation

    公开(公告)号:US11159112B2

    公开(公告)日:2021-10-26

    申请号:US16697630

    申请日:2019-11-27

    发明人: Matthias Preindl

    IPC分类号: H02P21/13 H02P21/18 H03H21/00

    摘要: Disclosed are implementations, including a method that includes obtaining measurement samples relating to electrical operation of an electric motor drive providing power to an electric motor, deriving, based on the samples, instantaneous estimates for parameters characterizing speed and/or position of the motor according to an optimization process based on a cost function defined for the samples, and applying a filtering operation to the instantaneous estimates to generate filtered values of the motor's speed and/or position. The filtering operation includes computing the filtered values using the derived instantaneous estimates in response to a determination that a computed convexity of the cost function is greater than or equal to a convexity threshold value, and/or applying a least-squares filtering operation to the derived instantaneous estimates and using at least one set of previous estimates derived according to the optimization process applied to previous measurement samples.

    Frequency response method and apparatus

    公开(公告)号:US11158341B2

    公开(公告)日:2021-10-26

    申请号:US16770609

    申请日:2018-12-12

    摘要: The invention provides a method and apparatus for filtering a temporal signal. A target magnitude frequency response HT(f) is specified (101,201) of frequency f in terms of a column vector l of K weights lk where log HT(f)=lTW(f) and W(f) is a column vector of K magnitude basis functions Wk(f). A constrained frequency response Hc(f) is computed (102,214) defined by log Hc(f)=gTV(f) , where V(f) is a column vector of N constrained basis functions Vn(f) for which each exp gnVn(f) satisfies a constraint preserved by concatenation, and g is a column vector of N coefficients satisfying a matching criterion between lTW(f) and gTV(f). An input temporal signal is received (103,212) and filtered (104,210) with the constrained frequency response Hc(f) to form a filtered temporal signal; and the filtered temporal signal is output (105,211).