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公开(公告)号：US12015385B2
公开(公告)日：2024-06-18
申请号：US17663015
申请日：2022-05-11
发明人： Tzu-Chieh Wei
CPC分类号： H03F3/183 , H03F2200/03 , H03F2200/165
摘要： Audio amplifier circuit includes a pulse width modulation circuit, an auxiliary loop circuit corresponding to a first variable resistance value and a first variable current value, and a main loop circuit corresponding to a second variable resistance value and a second variable current value. Main loop circuit is coupled between a second node, an output terminal, and a first node. Under a condition that auxiliary loop circuit and main loop circuit are turned on, second variable resistance value is decreased and second variable current value is increased after auxiliary loop circuit enters into a first control state, such that main loop circuit enters into a second control state. First variable resistance value is increased and first variable current value is decreased after main loop circuit enters into second control state, such that auxiliary loop circuit is out of first control state.
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公开(公告)号：US11990870B2
公开(公告)日：2024-05-21
申请号：US17687679
申请日：2022-03-07
发明人： Peter J. Holzmann
CPC分类号： H03F1/0205 , H03F3/217 , H03F2200/03
摘要： A class-D driver circuit includes a feedback loop including an input integrator stage, a switched modulator, and an output driver stage. A feedback resistor connects an output terminal of the output driver stage with an input node of the input integrator stage to provide a feedback current. The class-D driver circuit also includes a compensation circuit configured to provide a compensation current to an output node of the input integrator stage to relieve a slew rate limitation of the feedback loop, the compensation current having a magnitude based on the magnitude of the feedback current.
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公开(公告)号：US11689167B2
公开(公告)日：2023-06-27
申请号：US17812532
申请日：2022-07-14
申请人： Bose Corporation
发明人： Remco Terwal , Thomas Omar Powell
CPC分类号： H03F3/265 , H03F1/0244 , H03F3/45179 , H03G3/3026 , H04R3/00 , H03F3/2171 , H03F3/2173 , H03F2200/03
摘要： Various implementations include a common mode voltage controller for a self-boosting push pull amplifier. In some implementations, input signal are processed by: calculating, based upon the input signal, a maximum duty cycle to achieve a target differential in an output of the self-boosting push pull amplifier; calculating, based on the input signal, a set of control parameters associated with adjusting a common mode voltage of the output; and generating, based on the input signal, a pair of signals configured to adjust the common mode voltage of the output, wherein the pair of signals include a gain adjustment and offset based on the maximum duty cycle and the set of control parameters, and wherein the pair of signals are configured to maintain the target differential in the output of the self-boosting push pull amplifier as the common mode voltage is adjusted to a different operating point.
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公开(公告)号：US11689165B1
公开(公告)日：2023-06-27
申请号：US17562991
申请日：2021-12-27
发明人： Anthony Gribben
CPC分类号： H03F3/2173 , H03F3/187 , H03F2200/03
摘要： An adaptive sample and hold circuit for signal amplifier range selection is presented. The adaptive sample and hold circuit has an input for receiving an input signal and an output for providing a sample-and-hold-voltage. It also includes a sample-and-hold-capacitor to generate the sample-and-hold-voltage from the input signal, and a range detector. The range detector is adapted to identify a range of the input signal and to adjust a voltage at the sample-and-hold-capacitor based on the range of the input signal to maintain the sample-and-hold-voltage within a predetermined voltage span.
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公开(公告)号：US11552609B2
公开(公告)日：2023-01-10
申请号：US17189873
申请日：2021-03-02
发明人： John P. Lesso
摘要： The present disclosure relates to amplifier circuitry (300) that includes a linear amplifier stage (110) that receives an input signal and outputs a first drive signal to an output node (302) and a switching amplifier stage (130) operable to output a second drive signal to the output node (302). A controller (340) is selectively operable in a first dual-amplifier mode, in which switching of the switching amplifier stage is controlled based on a current of the first drive signal, such that the current of the first drive signal does not exceed a first current threshold magnitude; and at least one other mode, in which the controller controls the switching amplifier stage such that the current of the first drive signal may exceed the first current threshold magnitude. The controller (340) selectively controls the mode of operation based on an indication (SSL) of signal level of the output signal.
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公开(公告)号：US11489499B1
公开(公告)日：2022-11-01
申请号：US17396853
申请日：2021-08-09
发明人： Tsung-Fu Lin , Hsin-Yuan Chiu
摘要： A switch circuit provides a first output signal and a second output signal for switching between ternary modulation and quaternary modulation for a target device. A first output signal is provided from one of a first signal, a second signal and a ground signal according to an input signal and a duty signal, wherein the first signal is generated through performing a one-bit left-shift operation for the input signal, and the second signal is generated through adding the input signal and the duty signal. A second output signal is provided from one of a third signal, a fourth signal and the ground signal according to the input signal and the duty signal, wherein the third signal is generated through subtracting the input signal from the duty signal, and the fourth signal is generated through performing a two's-complement transformation and the one-bit left-shift operation for the input signal.
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公开(公告)号：US20220209727A1
公开(公告)日：2022-06-30
申请号：US17565795
申请日：2021-12-30
申请人： NSL COMM LTD
发明人： Uzi RAM , David MANSOUR
摘要： Systems and methods of multiport amplifier (MPA) implementation system, including: at least one input matrix, including a plurality of complex modulators, wherein each complex modulator is configured to receive an input channel stream, a summation logic block, configured to sum the complex product of the plurality of complex modulators, and a dual Digital to Analog (DAC) converter, configured to receive summation digital complex output from the summation logic block, a plurality of RF modulators, wherein each RF modulator is configured to receive a dual analog output as baseband I/Q branches from a corresponding DAC converter, and a plurality of amplifiers, wherein each complex amplifier is configured to receive the output of a corresponding RF Modulator for amplification to an output RF matrix.
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公开(公告)号：US11207534B2
公开(公告)日：2021-12-28
申请号：US16684270
申请日：2019-11-14
申请人： Pacesetter, Inc.
发明人： Kenneth J. Carroll
IPC分类号： A61N1/378 , A61N1/372 , H04B13/00 , A61N1/05 , A61N1/37 , A61N1/375 , A61N1/39 , H03F3/38 , H03F3/45
摘要： Disclosed herein are implantable medical devices (IMDs) including a receiver and a battery, and methods for use therewith. The receiver includes first and second differential amplifiers, each of which monitors for a predetermined signal within a frequency range and drains power from the battery while enabled, and while not enabled drains substantially no power from the battery. To remove undesirable input offset voltages, each of the differential amplifiers, while enabled, is selectively put into an offset correction phase during which time the predetermined signal is not detectable by the differential amplifier. At any given time at least one of the first and second differential amplifiers is enabled without being in the offset correction phase so that at least one of the differential amplifiers is always monitoring for the predetermined signal. In this manner, the receiver is never blind to signals, including the predetermined signals, sent by another IMD.
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公开(公告)号：US11057010B2
公开(公告)日：2021-07-06
申请号：US16711562
申请日：2019-12-12
申请人： NXP B.V.
发明人： Ghiath Al-kadi , Erich Merlin , Ulrich Neffe , Ludovic Oddoart
摘要： Embodiments of a power amplifier and method of operating a power amplifier are disclosed. In one embodiment, a power amplifier includes a pulse wave modulation (PWM) controller, a first power control stage configured to drive a first output between VDD and VSS in response to a control signal from the PWM controller, a second power control stage configured to drive a second output between VDD and VSS in response to a control signal from the PWM controller, and a mid-voltage control circuit configured to hold the voltage of the first output at a mid-voltage that is between VDD and VSS during an interval between when the first output is driven between VDD and VSS and hold the voltage of the second output at the mid-voltage during an interval between when the first output is driven between VDD and VSS.
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公开(公告)号：US10965279B2
公开(公告)日：2021-03-30
申请号：US16360927
申请日：2019-03-21
发明人： Yogesh Kumar Ramadass , Bhushan Talele , Shailendra Kumar Baranwal , Yinglai Xia , Junmin Jiang
摘要： A multi-level ramp generator comprises three ramp generators. The first ramp generator generates a first ramp signal, comprising a sawtooth voltage waveform with a first common mode voltage and a first peak to peak voltage. The second ramp generator generates a second ramp signal, comprising a sawtooth voltage waveform with a second common mode voltage and a second peak-to-peak voltage. The third ramp generator generates a third ramp signal, comprising a sawtooth voltage waveform with a third common mode voltage and the second peak-to-peak voltage. The second and third ramp signals are in phase with each other and the first ramp signal is 180° out of phase with the second and third ramp signals. In some implementations, each of the first, second, and third ramp generators comprise a respective delay locked loop and a respective voltage controlled oscillator.
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