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公开(公告)号：US10749473B2
公开(公告)日：2020-08-18
申请号：US15966747
申请日：2018-04-30
申请人： GLOBALFOUNDRIES INC.
摘要： An apparatus for performing a frequency multiplication of an mm-wave wave signal is provided. The apparatus includes a first differential circuit that is capable of receiving a 0° phase component of an input signal and a 180° phase component of the input signal having a first frequency. The first differential circuit provides a first output signal that is twice the frequency and is in −phase(0°) based on the 0° the 180° phase components of the input signal. The apparatus also includes a second differential circuit that is capable of receiving a 90° phase component of the input signal and a 270° phase component of the input signal, and provide a first output signal that is twice the frequency and out of phase(180°). The apparatus also includes a differential transformer that is configured to receive the first output signal and the second output signal. The differential transformer is configured to provide a differential output signal that has a second frequency that is twice the first frequency.
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公开(公告)号：US10069489B2
公开(公告)日：2018-09-04
申请号：US15598003
申请日：2017-05-17
申请人： Cemin Zhang
发明人： Cemin Zhang
摘要： The disclosure discloses a multiplexer based frequency extender comprising a preamplifier to receive a RF input signal and output a pre-amplified RF signal, at least one frequency multiplier or at least one frequency divider, and a multiplexer. The multiplexer comprises multiple differential pairs, each differential pair comprises a corresponding bias current control circuit that switches ON or OFF a bias current flowing through a corresponding differential pair. The at least one frequency multiplier or the at least one frequency divider receives the pre-amplified RF signal and outputs a frequency-multiplied RF signal or a frequency-divided signal. The multiplexer couples to receive the pre-amplified RF signal, the frequency-multiplied RF signal and/or the frequency-divided signal, the multiplexer selects a signal from the received signals and outputs based on the selected signal a multiplexer output signal.
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公开(公告)号：US08847638B2
公开(公告)日：2014-09-30
申请号：US12496875
申请日：2009-07-02
申请人： Ngar Loong Alan Chan , Shen Wang
发明人： Ngar Loong Alan Chan , Shen Wang
CPC分类号： H03K3/35613
摘要： A high frequency divider involves a plurality of differential latches. Each latch includes a pair of cross-coupled P-channel transistors and a variable resistance element. The latch is controlled to have a lower output resistance at high operating frequencies by setting a multi-bit digital control value supplied to the variable resistance element. Controlling the latch to have a reduced output resistance at high frequencies allows the 3 dB bandwidth of the latch to be maintained over a wide operating frequency range. The variable resistance element is disposed between the two differential output nodes of the latch such that appreciable DC bias current does not flow across the variable resistance element. As a consequence, good output signal voltage swing is maintained at high frequencies, and divider current consumption does not increase appreciably at high frequencies as compared to output signal swing degradation and current consumption increases in a conventional differential latch divider.
摘要翻译： 高分频器包括多个差分锁存器。 每个锁存器包括一对交叉耦合的P沟道晶体管和可变电阻元件。 通过设置提供给可变电阻元件的多位数字控制值，控制锁存器在高工作频率下具有较低的输出电阻。 控制锁存器在高频下具有降低的输出电阻允许在宽的工作频率范围内保持锁存器的3 dB带宽。 可变电阻元件设置在闩锁的两个差分输出节点之间，使得明显的直流偏置电流不流过可变电阻元件。 因此，与传统的差分锁存器分频器中的输出信号摆幅下降和电流消耗增加相比，良好的输出信号电压摆幅保持在高频，并且分频器电流消耗在高频下不会明显增加。
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公开(公告)号：US08115522B2
公开(公告)日：2012-02-14
申请号：US12765601
申请日：2010-04-22
申请人： Jia Chen
发明人： Jia Chen
CPC分类号： H03B19/14
摘要： A prescaler circuit according to an exemplary aspect of the present invention includes a first flip-flop circuit that detects second output data and outputs the detected data as first output data, and a second flip-flop circuit that detects the first output data and outputs the data as the second output data. The first flip-flop circuit includes a master-side latch circuit that generates intermediate data, a slave-side latch circuit that detects the intermediate data and outputs the data as the first output data, and a control signal switching circuit that selects and outputs the first output data as a control signal in a mode where the frequency is divided by 3, and selects and outputs a predefined fixed signal as a control signal in a mode where the frequency is divided by 4. The master-side latch circuit generates the intermediate data based on the second output data and the control signal.
摘要翻译： 根据本发明的示例性方面的预分频器电路包括：第一触发器电路，其检测第二输出数据并将检测到的数据作为第一输出数据输出;以及第二触发器电路，其检测第一输出数据并输出 数据作为第二输出数据。 第一触发器电路包括产生中间数据的主侧锁存电路，检测中间数据并输出数据作为第一输出数据的从侧锁存电路，以及控制信号切换电路，其选择并输出 第一输出数据作为频率被除以3的模式的控制信号，并且以频率被除以4的模式选择并输出预定义的固定信号作为控制信号。主侧锁存电路产生中间 基于第二输出数据和控制信号的数据。
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公开(公告)号：US20110254595A1
公开(公告)日：2011-10-20
申请号：US13087021
申请日：2011-04-14
申请人： Weigang Sun
发明人： Weigang Sun
CPC分类号： H03K3/356139 , H03K21/10 , H03K23/00
摘要： Various embodiments of a flip-flop and a frequency dividing circuit are provided. In one aspect, a flip-flop includes an input stage and a latch stage. The input stage is capable of converting an input signal to an output signal under the control of a first clock signal and a second clock signal. The latch stage is capable of latching the output signal under the control of a third clock signal and a fourth clock signal. The first clock signal, the second clock signal, the third clock signal and the fourth clock signal have different phases.
摘要翻译： 提供了触发器和分频电路的各种实施例。 一方面，触发器包括输入级和锁存级。 输入级能够在第一时钟信号和第二时钟信号的控制下将输入信号转换为输出信号。 锁存级能够在第三时钟信号和第四时钟信号的控制下锁存输出信号。 第一时钟信号，第二时钟信号，第三时钟信号和第四时钟信号具有不同的相位。
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公开(公告)号：US20110210767A1
公开(公告)日：2011-09-01
申请号：US12979684
申请日：2010-12-28
IPC分类号： H03B19/06
摘要： Phase-coherent differential structures contain a phase-coherent transformer having two pairs of phase-coherent coupled differential inductors.
摘要翻译： 相位相干差分结构包含具有两对相位相干耦合差分电感器的相位相干变压器。
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公开(公告)号：US20110001522A1
公开(公告)日：2011-01-06
申请号：US12496875
申请日：2009-07-02
申请人： Ngar Loong Alan Chan , Shen Wang
发明人： Ngar Loong Alan Chan , Shen Wang
CPC分类号： H03K3/35613
摘要： A high frequency divider involves a plurality of differential latches. Each latch includes a pair of cross-coupled P-channel transistors and a variable resistance element. The latch is controlled to have a lower output resistance at high operating frequencies by setting a multi-bit digital control value supplied to the variable resistance element. Controlling the latch to have a reduced output resistance at high frequencies allows the 3 dB bandwidth of the latch to be maintained over a wide operating frequency range. The variable resistance element is disposed between the two differential output nodes of the latch such that appreciable DC bias current does not flow across the variable resistance element. As a consequence, good output signal voltage swing is maintained at high frequencies, and divider current consumption does not increase appreciably at high frequencies as compared to output signal swing degradation and current consumption increases in a conventional differential latch divider.
摘要翻译： 高分频器包括多个差分锁存器。 每个锁存器包括一对交叉耦合的P沟道晶体管和可变电阻元件。 通过设置提供给可变电阻元件的多位数字控制值，控制锁存器在高工作频率下具有较低的输出电阻。 控制锁存器在高频下具有降低的输出电阻允许在宽的工作频率范围内保持锁存器的3 dB带宽。 可变电阻元件设置在闩锁的两个差分输出节点之间，使得明显的直流偏置电流不流过可变电阻元件。 因此，与传统的差分锁存器分频器中的输出信号摆幅下降和电流消耗增加相比，良好的输出信号电压摆幅保持在高频，并且分频器电流消耗在高频下不会明显增加。
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公开(公告)号：US07782101B2
公开(公告)日：2010-08-24
申请号：US12164117
申请日：2008-06-30
申请人： Sheng-Lyang Jang , Cheng-Chen Liu
发明人： Sheng-Lyang Jang , Cheng-Chen Liu
IPC分类号： H03B19/06
摘要： An injection-locked frequency divider for dividing a frequency of an injection signal and obtaining a frequency divided signal is provided. The injection-locked frequency divider includes a signal injection unit and an oscillator. The signal injection unit includes a first input terminal and a second input terminal for receiving the injection signal. The received injection signal exhibits a phase difference of 180° between the first input terminal and the second input terminal. The oscillator includes an inductor unit and a variable capacitance unit. The injection-locked frequency divider is featured with a wide injection locking range, and can be realized with a low operation voltage, and therefore can be conveniently used in different kinds of hybrid ICs.
摘要翻译： 提供了一种用于分割喷射信号的频率并获得分频信号的注入锁定分频器。 注入锁定分频器包括信号注入单元和振荡器。 信号注入单元包括用于接收注入信号的第一输入端和第二输入端。 所接收的注入信号在第一输入端和第二输入端之间呈现180°的相位差。 振荡器包括电感单元和可变电容单元。 注入锁定分频器具有宽注入锁定范围，可以实现低工作电压，因此可以方便地用于不同种类的混合IC。
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公开(公告)号：US07495484B1
公开(公告)日：2009-02-24
申请号：US11830445
申请日：2007-07-30
IPC分类号： H03B19/06
CPC分类号： H03D7/00
摘要： A programmable frequency multiplier device which includes a frequency doubler section configured to receive an input signal having a frequency f, and to output doubled signals, each of the doubled signals having a frequency 2n×f (n=0, 1, 2, . . . ); a selector section configured to select a plurality of the doubled signals output from the frequency doubler section, and to output the plurality of the selected doubled signals as selected signals; and a frequency summation section configured to multiply the selected signals, and to output a multiplied signal having a frequency fout=f×(m020+m121+ . . . +mk2k+ . . . +mn2n), wherein mk=0 or 1, and k=0, 1, . . . , n.
摘要翻译： 一种可编程倍频器装置，其包括被配置为接收具有频率f的输入信号的倍频器部分，并且输出双倍信号，每个双倍信号具有频率2nxf（n = 0,1,2，...） ; 选择器部分，被配置为选择从倍频器部分输出的多个双重信号，并将多个所选择的双倍信号作为选择信号输出; 以及频率求和部分，被配置为对所选择的信号进行乘法，并输出具有频率fout = fx（m020 + m121 + ... + mk2k + ... + mn2n）的相乘信号，其中mk = 0或1，并且k = 0，1，... 。 。 ，n。
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10.发明授权Apparatus for coherent generation of a radio frequency spectrum in amplitude and phase 失效无线电频谱在相位和相位上相互产生的装置
公开(公告)号：US3479602A
公开(公告)日：1969-11-18
申请号：US3479602D
申请日：1966-08-08
申请人： US ARMY
发明人： MORAR DONALD T
CPC分类号： H03B21/02
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