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公开(公告)号:US20240353916A1
公开(公告)日:2024-10-24
申请号:US18466101
申请日:2023-09-13
申请人: RTSync Corp.
发明人: Bernard ZEIGLER , Doohwan KIM
摘要: Embodiments disclose a DEVS chip is used to send only meaningful data in the system and therefore saves energy and increase processing speed. The sensor nodes communicate with an office chip temperature sensor or power management. The data acquired by the senor nodes is used for evaluating of the quantizer which has a stored quantum size and a stored temperature value or power level. If the difference between a stored temperature or a stored power level and a new temperature or a new stored power level is greater or equal to the predetermined quantum size, the new temperature or new power level is saved. The quantizer generates an event that transmits the temperature or the power level with quantum value to the sensor nodes. The small changes in the difference does not affect the system beyond the quantizer.
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公开(公告)号:US12111711B2
公开(公告)日:2024-10-08
申请号:US17402927
申请日:2021-08-16
申请人: Daedalus Prime LLC
IPC分类号: G06F1/32 , G06F1/20 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3287 , G06F1/329 , G06F9/50
CPC分类号: G06F1/3206 , G06F1/206 , G06F1/3203 , G06F1/3253 , G06F1/3287 , G06F1/329 , G06F9/5094 , G06F9/50 , Y02D10/00
摘要: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.
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公开(公告)号:US12105576B2
公开(公告)日:2024-10-01
申请号:US17581443
申请日:2022-01-21
申请人: Dell Products L.P.
发明人: Ian Roche , Philip Hummel , Dharmesh M. Patel
IPC分类号: G06F1/329
CPC分类号: G06F1/329
摘要: Techniques described herein relate to a method for optimizing power for a computer vision environment. The method includes obtaining, by a computer vision (CV) manager, an initial power optimization request associated with a CV workload; in response to obtaining the initial power optimization request: obtaining CV workload information associated with the CV workload; obtaining first CV environment configuration information associated with the power optimization request; generating a power optimization report based on the first CV environment configuration information and the CV workload information using a power optimization model; and initiating performance of the CV workload in a CV environment based on the power optimization report.
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公开(公告)号:US20240231470A9
公开(公告)日:2024-07-11
申请号:US18491689
申请日:2023-10-20
申请人: Intel Corporation
发明人: Efraim ROTEM , Eliezer WEISSMANN , Doron RAJWAN , Yoni AIZIK , Esfir NATANZON , Nir ROSENZWEIG , Nadav SHULMAN , Bart PLACKLE
CPC分类号: G06F1/329 , G06F9/4893
摘要: Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.
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公开(公告)号:US20240126359A1
公开(公告)日:2024-04-18
申请号:US18457057
申请日:2023-08-28
申请人: Tahoe Research, Ltd.
IPC分类号: G06F1/3287 , G06F1/3203 , G06F1/329 , G06F9/4401
CPC分类号: G06F1/3287 , G06F1/3203 , G06F1/329 , G06F9/4418 , G06F1/3209 , Y02D10/00 , Y02D30/50
摘要: The present invention relates to platform power management.
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公开(公告)号:US11934247B2
公开(公告)日:2024-03-19
申请号:US17250188
申请日:2019-06-06
申请人: SONY CORPORATION
发明人: Masatomo Kurata , Takashi Nitta , Futoshi Takeuchi , Kenji Suzuki
IPC分类号: G06F1/32 , G06F1/3209 , G06F1/3212 , G06F1/329 , G06F21/31 , G06F1/3203
CPC分类号: G06F1/3212 , G06F1/3209 , G06F1/329 , G06F21/31 , G06F1/3203
摘要: An information processing apparatus includes a communication unit capable of communicating with a server, a battery, and a controller. The controller is capable of executing processing regarding a predetermined function for which personal authentication is required at a time of use, detects a remaining charge level of the battery, and transmits, when the detected remaining charge level is less than a predetermined threshold value, a transfer request signal to the server, the transfer request signal requesting transfer of use authority of the function to another information processing apparatus.
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公开(公告)号:US20240036628A1
公开(公告)日:2024-02-01
申请号:US18482613
申请日:2023-10-06
发明人: Dong-Hee HAN , Dae-yeong Lee
IPC分类号: G06F1/324 , G06F15/78 , G06F1/329 , G06F1/3206 , G06F1/3234
CPC分类号: G06F1/324 , G06F15/7807 , G06F1/329 , G06F1/3206 , G06F1/3243
摘要: In a method of operating a system-on-chip (SOC), the SOC includes a plurality of processor cores. An operating frequency of the plurality of processor cores is set to a first operating frequency based on permitted power consumption of the SOC and an operating status of the plurality of processor cores. The first operating frequency is within a maximum operating frequency of the plurality of processor cores. At least one of the plurality of processor cores performs at least one processing operation based on the first operating frequency. When present power consumption of the SOC is determined as exceeding the permitted power consumption, a warning signal is activated, and a first control operation for reducing the present power consumption is performed immediately thereafter.
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公开(公告)号:US11880258B2
公开(公告)日:2024-01-23
申请号:US16923310
申请日:2020-07-08
发明人: Ulrich Stählin
IPC分类号: G06F1/3228 , G06F9/54 , B60K35/00 , G06F1/329 , G06F1/3296
CPC分类号: G06F1/3228 , B60K35/00 , G06F1/329 , G06F1/3296 , G06F9/542 , G06F9/546
摘要: A method for reducing processing power of a data processing hardware executing one or more applications is provided. The method includes receiving communication messages and identifying a first application outputting a first message based on at least one communication message. The first application is associated with a first priority value. The method includes determining a group of high-priority applications where each application has a priority value being higher than or equal to the first priority value and determining a group of low-priority applications where each application has a priority value being lower than the first priority value. The method includes discarding one or more communication messages that are not relied on by the group of high-priority applications for a predefined period of time. The method may also include sending, to the group of low-priority applications, instructions causing the one or more applications of the low-priority group to stop executing.
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9.
公开(公告)号:US11789520B1
公开(公告)日:2023-10-17
申请号:US18305624
申请日:2023-04-24
申请人: RTSync Corp.
发明人: Bernard Zeigler , Doohwan Kim
摘要: Embodiments disclose a DEVS chip is used to send only meaningful data in the system and therefore saves energy and increase processing speed. The sensor nodes communicate with an office chip temperature sensor or power management. The data acquired by the senor nodes is used for evaluating of the quantizer which has a stored quantum size and a stored temperature value or power level. If the difference between a stored temperature or a stored power level and a new temperature or a new stored power level is greater or equal to the predetermined quantum size, the new temperature or new power level is saved. The quantizer generates an event that transmits the temperature or the power level with quantum value to the sensor nodes. The small changes in the difference does not affect the system beyond the quantizer.
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公开(公告)号:US11775047B2
公开(公告)日:2023-10-03
申请号:US17879256
申请日:2022-08-02
申请人: INTEL CORPORATION
发明人: Jianfang Zhu , Deepak Samuel Kirubakaran , Raoul Rivas Toledano , Chee Lim Nge , Rajshree Chabukswar , James Hermerding, II , Sudheer Nair , William Braun , Zhongsheng Wang , Russell Fenger , Udayan Kapaley
IPC分类号: G06F1/32 , G06F1/329 , G06F1/3228 , G06F9/38 , G06F9/48
CPC分类号: G06F1/329 , G06F1/3228 , G06F9/3836 , G06F9/4812 , G06F9/4893
摘要: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.
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