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公开(公告)号：US12124290B2
公开(公告)日：2024-10-22
申请号：US17913454
申请日：2021-03-26
申请人： dSPACE GmbH
发明人： Dominik Lubeley , Marc Schlenger , Paul Gruber
摘要： A method for inputting and/or outputting signals having a selectable sample rate in a time-synchronized manner on a group of input and/or output channels of an electronic circuit includes: configuring each channel of the group at a standard sample period; synchronously initiating all the channels of the group at the standard sample period; detecting an entry for a modified sample period TPeriod of a first channel of the group; detecting a current counter value TCounter; configuring the first channel at the modified sample period; establishing a waiting time of TWaiting clocks in accordance with TWaiting=TPeriod−mod(TCounter, TPeriod), where mod (TCounter, TPeriod) denotes the division remainder from the current counter value TCounter and the modified sample period TPeriod; and initiating the first channel after the waiting time TWaiting.
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公开(公告)号：US12124026B2
公开(公告)日：2024-10-22
申请号：US18153026
申请日：2023-01-11
发明人： Ping Liu
CPC分类号： G02B26/06 , G02B27/0172 , G06F1/12 , G06F1/14 , G06T19/006
摘要： A master clock signal for an image capture device and a light emission device is accessed. The master clock signal is divided to generate a high frequency clock signal. A frame timer is used to measure a frame time of the image capture device based on cycles of the high frequency clock signal. Based on an exposure timing signal from the image capture device, estimating an exposure start time for the image capture device; is estimated. Based on the estimated starting time, the light emission device begins emission of a positional tracking pattern at the estimated starting time and for a duration determined by the measured frame time of the image capture device.
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公开(公告)号：US12111682B2
公开(公告)日：2024-10-08
申请号：US18026014
申请日：2020-09-14
申请人： LG ELECTRONICS INC.
发明人： Jongin Choi
摘要： The present disclosure relates to a delay synchronization processing apparatus and a signal processing apparatus provided with same. The delay synchronization processing apparatus according to one embodiment of the present disclosure comprises: a delay device to generate a random number and to delay an input asynchronous N-bit signal based on the generated random number; and a synchronization processor configured to perform synchronization processing on the asynchronous N-bit signal delayed by the delay device. Accordingly, errors during non-synchronous bit signal processing can be detected.
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公开(公告)号：US20240329931A1
公开(公告)日：2024-10-03
申请号：US18617685
申请日：2024-03-27
摘要： A signal processing method includes: an analysis object data generation step of generating i-th analysis object data based on time-series data of a physical quantity detected by an i-th sensor; a product-sum operation step of generating product-sum operation data of template data including a signal component to be analyzed and M-th analysis object data; and a synchronous-timing detection step of detecting a synchronous timing, which is timing synchronizing with the signal component, based on the product-sum operation data. The template data is shorter than the M-th analysis object data, and a sampling rate of the M-th analysis object data is equal to a sampling rate of the template data.
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公开(公告)号：US20240329838A1
公开(公告)日：2024-10-03
申请号：US18129300
申请日：2023-03-31
发明人： Aaron D. Willey
CPC分类号： G06F3/0611 , G06F1/12 , G06F3/0634 , G06F3/0653 , G06F3/0659 , G06F3/0673
摘要： A data processing system includes a data processor having a memory controller, and a memory. The memory is coupled to the memory controller and is for reading and writing data synchronously with respect to a clock signal. The memory includes a sensor circuit that is responsive to a control signal to output a measured value without using the clock signal.
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公开(公告)号：US12105552B2
公开(公告)日：2024-10-01
申请号：US17919039
申请日：2021-04-14
发明人： Nobuyasu Shiga , Satoshi Yasuda
IPC分类号： G06F1/12
CPC分类号： G06F1/12
摘要： It is provided a synchronization system capable of managing execution of synchronization for clocks to be mounted on various devices.
A synchronization system of clocks comprising: a leader device; a follower device capable of establishing communication connection with the leader device; and a server apparatus capable of establishing communication connection with the leader device and/or the follower device, the system further comprising: a time deviation calculator configured to calculate a time deviation between the leader device and the follower device; and a time corrector configured to correct a time in the follower device based on the calculated time deviation, wherein the synchronization system executes the time deviation calculator and/or the time corrector when the server apparatus generates, transmits, and/or receives predetermined information.-
公开(公告)号：US12079029B2
公开(公告)日：2024-09-03
申请号：US17313026
申请日：2021-05-06
发明人： Itai Levy , Dotan David Levi , Nir Nitzani , Natan Manevich , Alex Vaynman , Ariel Almog
CPC分类号： G06F1/12 , G06F13/20 , H04L7/0012
摘要： A network adapter includes a network port for communicating with a communication network, a hardware clock, and circuitry. The circuitry is coupled to receive from the communication network, via the network port, one or more time-protocol packets that convey a network time used for synchronizing network devices in the communication network, to align the hardware clock to the network time conveyed in the time-protocol packets, and to make the network time available to one or more time-service consumers running in a host served by the network adapter.
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公开(公告)号：US12057193B2
公开(公告)日：2024-08-06
申请号：US18111925
申请日：2023-02-21
发明人： Hye-Ran Kim , Seong-Hwan Jeon , Tae-Young Oh
IPC分类号： G06F1/12 , G06F13/16 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4093
CPC分类号： G11C7/222 , G06F1/12 , G06F13/1689 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C11/4076 , G11C11/4093 , G11C2207/2254
摘要： A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.
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公开(公告)号：US20240255982A1
公开(公告)日：2024-08-01
申请号：US18344087
申请日：2023-06-29
发明人： Jaspal Singh Shah , Atul Katoch
摘要： Circuits and methods are provided for a clock generation circuit that includes a first transistor, wherein a gate of the first transistor is connected to a clock signal, a second transistor, connected in parallel to the first transistor, and a driving circuit, coupled to the second transistor, and comprising an input and an output, wherein the input of the driving circuit is connected to the clock signal, the output of the driving circuit is connected to a gate of the second transistor, and the driving circuit is configured to reduce a slew of the clock signal.
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公开(公告)号：US12050486B1
公开(公告)日：2024-07-30
申请号：US17805672
申请日：2022-06-06
发明人： Guy Nakibly , Moshe Raz , Zvika Glaubach , Moshe Noah
CPC分类号： G06F1/12
摘要： Techniques for cooperative timing alignment using synchronization pulses are described. The techniques can include generating, at an integrated circuit device, a timing signal, controlling a local count value based on the timing signal, monitoring a synchronization signal of a system comprising the integrated circuit device, detecting a synchronization pulse in the synchronization signal, and aligning the local count value with an implied count value associated with the synchronization pulse in order to align the local count value with those of other integrated circuit devices of the system.
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