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1.发明申请公开(公告)号：US20250022154A1
公开(公告)日：2025-01-16
申请号：US18902400
申请日：2024-09-30
Inventor： Xu XU , Biqiang HUANG , Shanshan XU , Wenchao WANG , Jixiang CHEN , Longgan HU
Abstract: An initial display substrate comprising a product region and a to-be-processed region on periphery of the product region, the to-be-processed region comprising to-be-processed rounded corner regions at corners of the initial display substrate, each corner comprising major corner sides whose extension directions intersect, at least one to-be-processed rounded corner region comprising first positioning sub-region and two second positioning sub-regions, the major corner sides respectively defining edges of the second positioning sub-regions, the first positioning sub-region being between the second positioning sub-regions; first shielding blocks in the first positioning sub-region, each having arc shape protruding towards direction away from the product region, and the first shielding blocks being arranged in parallel at intervals; and second shielding blocks in each second positioning sub-region, a shape of the second shielding block is not exactly the same as that of the first shielding block.
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公开(公告)号：US20240288376A1
公开(公告)日：2024-08-29
申请号：US18023810
申请日：2022-03-01
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Xing Li , Ruize Li , Hao Tang , Ronghua Lan , Jiuyang Cheng , Meng Guo , Zhihui Yang , Qing Zhang , Xuehui Zhu , Quanguo Zhou , Lijia Zhou , Yong Qiao , Zhong Huang , Lirong Xu
CPC classification number: G01N21/8851 , G01N21/892 , G06T7/0004 , G06T7/13 , G06V10/44 , G01N2021/8887 , G01N2021/891 , G01N2201/0438 , G01N2201/06146 , G06T2207/30108 , H10K71/70
Abstract: A curved substrate bubble detection method includes: providing, by a first light source and a second light source, parallel light incident to a to-be-tested substrate in different incident directions; obtaining, by a linear array camera, a first image including image information of a first side edge of the to-be-tested substrate; determining location information of a defect region of the to-be-tested substrate according to the first image, and generating a second image including image information of the defect region; binarizing the second image, and determining that the to-be-tested substrate has a bubble defect if there are at least two bright spots in an obtained binarized image, and a distance between any two first bright spots of at least two first bright spots is less than a first preset value. A curved substrate bubble detection system is also disclosed.
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公开(公告)号：US20240276860A1
公开(公告)日：2024-08-15
申请号：US18436096
申请日：2024-02-08
Applicant: Japan Display Inc.
Inventor： Sho YANAGISAWA , Hiroshi TABATAKE , Kota MAKISHI , Kazuyuki ENDOU
IPC: H10K71/70 , H10K59/131 , H10K59/80
CPC classification number: H10K71/70 , H10K59/131 , H10K59/871
Abstract: According to one embodiment, a mother substrate for a display device includes an inspection portion. The inspection portion includes first, second, third and fourth pads, a first line portion connected to the first pad, a second line portion connected to the second pad, a third line portion connected to the third pad and the fourth pad and including a middle portion, a first partition connected to the middle portion, a second partition surrounding the first partition, an organic layer provided between the first partition and the second partition, and an upper electrode which covers the organic layer. The upper electrode is in contact with a lower portion of the first partition and a lower portion of the second partition.
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公开(公告)号：US12058924B2
公开(公告)日：2024-08-06
申请号：US16981938
申请日：2019-12-23
IPC: H10K71/70 , G02F1/1362 , G02F1/1368 , G09G3/00 , H01L29/786 , H10K71/00
CPC classification number: H10K71/70 , G02F1/1368 , G09G3/006 , H01L29/78651 , H10K71/00 , G02F1/136254
Abstract: A test substrate has at least one test region and includes a base substrate, a plurality of thin film transistors disposed on the base substrate, at least one test hole located in the test region, and at least one test pin. At least one of the thin film transistors is a target thin film transistor to be tested, each target thin film transistor is located in one test region. Each test hole exposes a source region, a drain region or a gate of a corresponding target thin film transistor at a bottom thereof. Each test pin is located in one test hole. One end of the test pin passes through the test hole to be coupled to the source region, the drain region or the gate of the corresponding target thin film transistor, and another end of the test pin is exposed at a surface of the test substrate.
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5.发明授权公开(公告)号：US12022722B2
公开(公告)日：2024-06-25
申请号：US17555181
申请日：2021-12-17
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Beomjun Cheon , Kyungsik Kim , Yun-seok Eo , Sang-geun Lee , Seungkuk Lee , Sehee Lim , Jinsoo Choi
IPC: H10K71/00 , G09G3/00 , H01L21/66 , H01L21/67 , H01L21/78 , H01L23/544 , H10K50/84 , H10K50/844 , H10K59/12 , H10K59/131 , H10K71/70 , H10K102/00
CPC classification number: H10K71/00 , H01L21/67092 , H01L21/67259 , H01L23/544 , H10K50/844 , H10K59/131 , H10K71/70 , G09G3/006 , H01L22/12 , H01L2223/54426 , H01L2223/5448 , H10K59/1201 , H10K71/851 , H10K2102/351
Abstract: A method for manufacturing a display device is provided. A process of forming an inspection pattern, in which a protective film unit is partially removed in a thickness direction, in a pad area portion of the protective film unit, which corresponds to a pad area of a display unit, may be performed, and then, a process of delaminating the pad area portion of the protective film unit may be performed. A process of checking whether the inspection pattern exists may be performed to check whether the delamination has succeeded, and, at the same time, a process of measuring distances from an alignment mark to each of a long side and a short side of the display unit may be performed.
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Patent Agency Ranking
公开(公告)号：US11980085B2
公开(公告)日：2024-05-07
申请号：US17378599
申请日：2021-07-16
Applicant: Samsung Display Co., Ltd.
Inventor： Ho Seok Han
IPC: G09G3/3225 , G06F3/038 , G09G3/00 , G09G3/20 , H01L21/66 , H01L27/12 , H10K59/131 , H10K71/00 , H10K71/70
CPC classification number: H10K71/70 , G06F3/038 , G09G3/006 , G09G3/20 , G09G3/3225 , H01L22/14 , H01L22/34 , H01L27/1259 , H10K59/131 , H10K71/00 , G09G2300/0426 , G09G2310/0275 , G09G2330/045 , G09G2330/12
Abstract: A display device includes a sensing line and a data driver. The sensing line is in a display panel. The data driver includes a plurality of integrated circuits. Each of the integrated circuits includes an interface, which includes a mobile industry processor interface (MIPI) and a crack detector. The crack detector detects cracks of the panel based on the sensing line and transmits and receives information corresponding to the crack to and from adjacent ones of the integrated circuits using a transmission terminal and a reception terminal in the MIPI.
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公开(公告)号：US20240032358A1
公开(公告)日：2024-01-25
申请号：US18310594
申请日：2023-05-02
Applicant: Samsung Display Co., Ltd.
Inventor： DONG-YOUB LEE , KYUNG-MOK LEE , HEESOOK YOON
IPC: H10K59/131 , H10K71/70 , G06T7/00 , G06T7/70
CPC classification number: H10K59/131 , H10K71/70 , G06T7/0004 , G06T7/70
Abstract: A display device includes a display panel and a driving circuit chip. The driving circuit chip includes a signal bump and an alignment bump. The display panel includes a pixel disposed in a display area, a signal pad disposed in a non-display area and corresponding to the signal bump, an alignment pad disposed in the non-display area and corresponding to the alignment bump, a reference pad that is disposed in the non-display area, is spaced apart from the alignment pad, and does not overlap the driving circuit chip in a plan view, and a signal line disposed in the display area and the non-display area and electrically connecting the pixel and the signal pad.
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公开(公告)号：US11800781B2
公开(公告)日：2023-10-24
申请号：US18060930
申请日：2022-12-01
Applicant: Kateeva, Inc.
Inventor： Doris Pik-Yiu Chun , Ian David Parker
CPC classification number: H10K71/70 , G06T7/001 , G06T7/0004 , G06T7/0008 , G06T11/001 , G06T11/206 , G06T11/60 , H10K50/844 , G06T2200/24 , G06T2207/10024 , G06T2207/10028 , G06T2207/20072 , G06T2207/20224 , G06T2207/30121 , G06T2207/30148 , H10K71/135
Abstract: A method of analyzing film on a substrate comprises receiving surface profile data obtained from measurements of a substrate having a plurality of discrete regions with one or more film layers; extracting, based on a predetermined pattern of the discrete regions, a plurality of parameters from the received surface profile data, the plurality of parameters comprising one or more parameters of a film layer of each discrete regions, and displaying a user interface. The user interface may comprise a plurality of individual graphs each illustrating the one or more parameters of the one or more film layers for a corresponding subset of the plurality of discrete regions, and a composite graph illustrating the one or more parameters of the one or more film layers for each discrete region of the plurality of discrete regions, wherein the composite graph corresponds to the plurality of individual graphs being overlaid together.
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公开(公告)号：US11672149B2
公开(公告)日：2023-06-06
申请号：US16910766
申请日：2020-06-24
Inventor： Guangyao Li , Dongfang Wang , Jun Wang , Haitao Wang , Qinghe Wang , Ning Liu , Wei Li , Yingbin Hu , Yang Zhang
IPC: H10K59/131 , H10K71/70 , H10K71/00 , H10K102/00 , H01L27/32 , H01L51/00 , H01L51/56
CPC classification number: H01L27/3276 , H01L51/0031 , H01L51/56 , H01L2251/5392 , H01L2251/568
Abstract: The present disclosure provides an OLED display panel and a method for detecting the OLED display panel, and a display device. The OLED display panel includes a base substrate including a display area and a non-display area surrounding the display area and having a first region adjacent to the display area. The display area includes a drive signal line and a power supply voltage signal line both extending from the display area to the first region. The drive signal line includes, in the first region, a first section of wiring at an anode layer, the power supply voltage signal line includes, in the first region, a second section of wiring at a gate metal layer, and parts of the drive signal line and the power supply voltage signal line in the display area are located at a source-drain metal layer.
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10.发明公开公开(公告)号：US20230171998A1
公开(公告)日：2023-06-01
申请号：US17921898
申请日：2021-06-01
Inventor： Yong ZHUO , Yanxia XIN , Hongwei HU , Zheng BAO , Xueping LI , Yihao WU , Xiaoyun WANG , Zhongqian GUO
IPC: H10K59/121 , H10K71/70 , H10K59/12 , H10K59/131
CPC classification number: H10K59/1213 , H10K71/70 , H10K59/1216 , H10K59/1201 , H10K59/131
Abstract: Provided are a display substrate, a testing method therefor and a preparation method therefor, and a display panel, which are used for improving the success rate of transistor testing. The display substrate comprises a base substrate and a pixel circuit, wherein the pixel circuit comprises an active layer, a first gate insulating layer, a first gate electrode layer, a second gate insulating layer, a second gate electrode layer, a first interlayer insulating layer, a source/drain electrode layer, and a second interlayer insulating layer. The pixel circuit is divided into a plurality of transistors, and further comprises a gate electrode contact hole and a source/drain electrode contact hole. The source/drain electrode layer comprises a gate electrode test pad which is electrically connected to the first gate electrode layer by means of the gate electrode contact hole, and a source electrode and a drain electrode which are electrically connected to the active layer by means of the source/drain electrode contact hole. The second interlayer insulating layer is provided with a gate electrode test hole and a source/drain electrode test hole, wherein the gate electrode test hole exposes the gate electrode test pad, and the source/drain electrode test hole exposes part of an area in the source/drain electrode layer other than the gate electrode test pad.
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