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    Interface discovery between partitions of a programmable logic device
    3.
    发明授权
    Interface discovery between partitions of a programmable logic device 有权

    公开(公告)号：US11301415B2

    公开(公告)日：2022-04-12

    申请号：US15862249

    申请日：2018-01-04

    申请人： Intel Corporation

    发明人： Evan Custodio

    IPC分类号： H03K19/17756 ,  G06F15/78 ,  H03K19/0175 ,  H03K19/17736 ,  G06F30/34

    摘要： Systems, methods, and devices for enhancing the flexibility of an integrated circuit device with partially reconfigurable regions are provided. For example, a discovery interface may determine and/or communicate a suitable logical protocol interface to control data transfer between regions on the integrated circuit device. The techniques provided herein result in more flexible partial reconfiguration options to enable greater compatibility between accelerator hosts and accelerator function units.

    Fast boot systems and methods for programmable logic devices
    4.
    发明授权
    Fast boot systems and methods for programmable logic devices 有权

    公开(公告)号：US11132207B2

    公开(公告)日：2021-09-28

    申请号：US16228647

    申请日：2018-12-20

    申请人： Lattice Semiconductor Corporation

    发明人： Fulong Zhang ,  Gordon Hands ,  Satwant Singh ,  Wei Han ,  Ravindar Lail ,  Joel Copien ,  Sreepada Hegade ,  Ming Hui Ding

    IPC分类号： G06F9/4401 ,  G06F3/06 ,  G06F9/445 ,  G06F21/57 ,  H03K19/17756 ,  H03K19/17758

    摘要： Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes receiving configuration data associated with a PLD. The PLD includes an array of configuration memory cells including logic block memory cells and input/output (I/O) block memory cells associated with the PLD's logic fabric and I/O fabric, respectively. The method further includes programming a subset of the I/O block memory cells with the configuration data, and providing a wakeup signal to activate functionality associated with a portion of the I/O fabric. The method further includes programming remaining configuration memory cells of the array with the configuration data, where the remaining configuration memory cells include at least a subset of the logic block memory cells. The method further includes providing a wakeup signal to activate functionality associated with at least a portion of the logic fabric. Related systems and devices are provided.

    METHOD AND APPARATUS FOR IMPLEMENTING CONFIGURABLE STREAMING NETWORKS
    6.
    发明申请
    METHOD AND APPARATUS FOR IMPLEMENTING CONFIGURABLE STREAMING NETWORKS 审中-公开

    公开(公告)号：US20200228121A1

    公开(公告)日：2020-07-16

    申请号：US16833206

    申请日：2020-03-27

    申请人： Altera Corporation

    发明人： Doris Tzu Lang Chen ,  Deshanand Singh

    IPC分类号： H03K19/17756

    摘要： A method of configuring a programmable integrated circuit device. A channel source within the virtual fabric is configured to receive input data from a first kernel outside of the virtual fabric and on the programmable integrated circuit device, and a channel sink within the virtual fabric is configured to transmit output data to the first kernel. The configuring of the channel source is modified such that the channel source receives input data from a second kernel in response to detecting a change in operation of the programmable integrated circuit device.

    Reconfigurable programmable integrated circuit with on-chip network
    7.
    发明授权
    Reconfigurable programmable integrated circuit with on-chip network 有权

    公开(公告)号：US10707875B1

    公开(公告)日：2020-07-07

    申请号：US16409191

    申请日：2019-05-10

    申请人： Achronix Semiconductor Corporation

    发明人： Kent Orthner ,  Travis Johnson ,  Sarma Jonnavithula

    IPC分类号： G06F13/20 ,  H03K19/17736 ,  H03K19/17756 ,  H03K19/1776 ,  G06F13/42 ,  G06F7/58

    摘要： Methods, systems, and computer programs are presented for routing packets on a network on chip (NOC) within a programmable integrated circuit. One programmable integrated circuit comprises a plurality of clusters disposed on a plurality of cluster rows and a plurality of cluster columns, an internal network on chip (iNOC) comprising iNOC rows and iNOC columns, an external network on chip (eNOC) connected to the iNOC rows and the iNOC columns, and a field programmable gate array Control Unit (FCU) for configuring programmable logic in the plurality of clusters based on a first configuration received by the FCU. The FCU is connected to the eNOC, where the FCU communicates with the plurality of clusters via the iNOC and the eNOC. The FCU is configured for receiving a second configuration from the programmable logic in the plurality of clusters for reconfiguring a component of the programmable integrated circuit.