公开(公告)号：US11132207B2

公开(公告)日：2021-09-28

申请号：US16228647

申请日：2018-12-20

申请人： Lattice Semiconductor Corporation

发明人： Fulong Zhang ,  Gordon Hands ,  Satwant Singh ,  Wei Han ,  Ravindar Lail ,  Joel Copien ,  Sreepada Hegade ,  Ming Hui Ding

IPC分类号： G06F9/4401 ,  G06F3/06 ,  G06F9/445 ,  G06F21/57 ,  H03K19/17756 ,  H03K19/17758

摘要： Various techniques are provided to implement fast boot for programmable logic devices (PLDs). In one example, a method includes receiving configuration data associated with a PLD. The PLD includes an array of configuration memory cells including logic block memory cells and input/output (I/O) block memory cells associated with the PLD's logic fabric and I/O fabric, respectively. The method further includes programming a subset of the I/O block memory cells with the configuration data, and providing a wakeup signal to activate functionality associated with a portion of the I/O fabric. The method further includes programming remaining configuration memory cells of the array with the configuration data, where the remaining configuration memory cells include at least a subset of the logic block memory cells. The method further includes providing a wakeup signal to activate functionality associated with at least a portion of the logic fabric. Related systems and devices are provided.