公开(公告)号：US06699790B2

公开(公告)日：2004-03-02

申请号：US10035807

申请日：2002-01-04

Applicant: Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Gil-Heyun Choi

Inventor： Byung-Hee Kim ,  Jong-Myeong Lee ,  Myoung-Bum Lee ,  Gil-Heyun Choi

IPC: H01L21443

CPC classification number: H01L21/76876 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76882

Abstract: A semiconductor device fabrication method having a recess region in an insulation layer on a silicon substrate, includes the steps of depositing a barrier metal on an entire surface of the insulation layer, filling the recess region with an oxide layer, removing the barrier metal on an upper side of the insulation layer, removing the oxide layer in the recess region and exposing the barrier metal of the recess region, depositing a CVD-Al layer on the barrier metal, and depositing a PVD-Al layer on the CVD-Al layer and re-flowing the PVD-Al layer. The fabrication method of a semiconductor integrated circuit according to the present invention selectively removes a barrier metal in the outside of the recess region to expose the insulation layer to the air, and deposits the CVD-Al layer and the PVD-Al layer, which results in controlling abnormal growth of the CVD-Al metal.

Abstract translation: 一种在硅衬底上的绝缘层中具有凹陷区域的半导体器件制造方法，包括以下步骤：在绝缘层的整个表面上沉积阻挡金属，用氧化物层填充该凹陷区域， 去除所述凹陷区域中的氧化物层并暴露所述凹陷区域的阻挡金属，在所述阻挡金属上沉积CVD-Al层，以及在所述CVD-Al层上沉积PVD-Al层，以及 重新流动PVD-Al层。 根据本发明的半导体集成电路的制造方法选择性地去除凹陷区域的外部的阻挡金属以将绝缘层暴露于空气，并沉积CVD-Al层和PVD-Al层，这导致 控制CVD-Al金属的异常生长。

公开(公告)号：US06465348B1

公开(公告)日：2002-10-15

申请号：US09875506

申请日：2001-06-06

Applicant: Yu-Piao Wang

Inventor： Yu-Piao Wang

IPC: H01L21443

CPC classification number: H01L21/76862 ,  H01L21/28556 ,  H01L21/76843

Abstract: A MOCVD is performed to form a titanium nitride layer on the surface of a semiconductor substrate. Following that, a pulsed plasma treatment is performed to remove hydro-carbon impurities from the titanium nitride layer. Therein, the pulsed plasma treatment is performed in a pressure chamber comprising nitrogen gas (N2) hydrogen gas (H2) or argon gas (Ar). A pressure of the pressure chamber is controlled to between 1 to 3 Torr, with the power of the pressure chamber controlled to between 500 and 1000 watts.

Abstract translation: 执行MOCVD以在半导体衬底的表面上形成氮化钛层。 之后，进行脉冲等离子体处理以从氮化钛层去除氢碳杂质。 其中，脉冲等离子体处理在包含氮气（N 2）氢气（H 2）或氩气（Ar）的压力室中进行。 压力室的压力控制在1至3托之间，压力室的功率控制在500至1000瓦特之间。

公开(公告)号：US06568978B2

公开(公告)日：2003-05-27

申请号：US09814168

申请日：2001-03-22

Applicant: Yoshiharu Kataoka ,  Takashi Fujikawa ,  Masafumi Kokura

Inventor： Yoshiharu Kataoka ,  Takashi Fujikawa ,  Masafumi Kokura

IPC: H01L21443

CPC classification number: G02F1/13439

Abstract: A method for producing an electrode substrate, having an organic insulating region formed of an organic insulating material and an inorganic insulating region formed of an inorganic insulating material on an identical side thereof, includes the steps of performing a plasma treatment of the organic insulating region; forming a first transparent conductive layer in contact with the organic insulating region and a second transparent conductive layer in contact with the inorganic insulating region; and etching the first transparent conductive layer and the second transparent conductive layer in the same step.

Abstract translation: 一种具有由有机绝缘材料形成的有机绝缘区域和在其同一侧由无机绝缘材料形成的无机绝缘区域的电极基板的制造方法，包括以下步骤：对有机绝缘区域进行等离子体处理; 形成与有机绝缘区域接触的第一透明导电层和与无机绝缘区域接触的第二透明导电层; 并在同一步骤中蚀刻第一透明导电层和第二透明导电层。

公开(公告)号：US06498095B2

公开(公告)日：2002-12-24

申请号：US09943045

申请日：2001-08-30

Applicant: Kazunori Matsuura

Inventor： Kazunori Matsuura

IPC: H01L21443

CPC classification number: H01L21/28556 ,  H01L21/76877 ,  Y10S438/913

Abstract: The interconnection system of the present invention comprises an interconnection film formed by chemical vapor deposition, wherein the interconnection film comprises an upper layer and a lower layer in which the concentrations of impurities are different. The method of producing an interconnection film comprising an upper layer and a lower layer by chemical vapor deposition using a single chamber, comprises: a lower layer forming step of depositing the lower layer in a recesses by evacuating the chamber and by injecting a reactant gas into the chamber; a cleaning step of subsequently reducing the partial pressure of impurities which are dissociated from the reactant gas; and an upper layer forming step of subsequently depositing an upper layer onto the lower layer by injecting a reactant gas into the chamber.

Abstract translation: 本发明的互连系统包括通过化学气相沉积形成的互连膜，其中互连膜包括杂质浓度不同的上层和下层。 通过使用单个室的化学气相沉积制造包括上层和下层的互连膜的方法包括：下层形成步骤，通过抽空室并将反应物气体注入 房间 随后降低与反应气体分离的杂质的分压的清洗步骤; 以及上层形成步骤，通过将反应气体注入到所述室中，随后将上层沉积到下层上。

公开(公告)号：US06573180B2

公开(公告)日：2003-06-03

申请号：US10101776

申请日：2002-03-21

Applicant: Jai Hyung Won

Inventor： Jai Hyung Won

IPC: H01L21443

CPC classification number: C23C16/45512 ,  C23C16/42 ,  C23C16/4401

Abstract: A semiconductor substrate having a polysilicon layer is loaded into a process chamber of a plasma enhanced chemical vapor deposition device. A silicon source gas, a tungsten source gas, and a hydrogen compound gas for reducing a chlorine radical are introduced into the process chamber, to thereby deposit the tungsten silicide layer on the polysilicon layer. The chlorine radical of the silicon source gas is reduced into hydrogen chloride by the hydrogen compound gas and is removed together with an exhaust gas.

Abstract translation: 具有多晶硅层的半导体衬底被装载到等离子体增强化学气相沉积装置的处理室中。 将硅源气体，钨源气体和用于还原氯自由基的氢化合物气体引入到处理室中，从而将硅化钨层沉积在多晶硅层上。 硅源气体的氯自由基通过氢化合物气体还原成氯化氢，并与废气一起除去。

公开(公告)号：US06458694B2

公开(公告)日：2002-10-01

申请号：US09767145

申请日：2001-01-23

Applicant: Naoaki Ogure ,  Takao Kato ,  Kuniaki Horie ,  Yuji Araki

Inventor： Naoaki Ogure ,  Takao Kato ,  Kuniaki Horie ,  Yuji Araki

IPC: H01L21443

CPC classification number: H01L21/76873 ,  C23C14/046 ,  C23C14/35 ,  H01J37/3405 ,  H01L21/2855 ,  H01L21/76877

Abstract: The present invention relates to a method and apparatus for forming interconnects on a substrate such as a semiconductor wafer by filling a conductive material such as copper (Cu) in fine recesses formed in a surface of the substrate. A method for forming interconnects comprises providing a substrate and a target composed of a conductive material in confrontation with each other in a chamber, introducing a sputtering gas into the chamber while a high voltage is applied between the substrate and the target to cause the sputtering gas to collide with the target, and depositing particles of the conductive material emitted from the target on the surface of the substrate to form a thin film, while sputter-etching the thin film by reflection sputtering gas molecules reflected from the target and having high energy.

Abstract translation: 本发明涉及一种在诸如半导体晶片的衬底上形成互连的方法和装置，该方法和装置通过在衬底的表面中形成的精细凹槽中填充诸如铜（Cu）的导电材料。 一种用于形成互连的方法包括在室内相互对置地提供由导电材料构成的基板和靶，将溅射气体引入室中，同时在基板和靶之间施加高电压以引起溅射气体 与目标物碰撞，在基板的表面上沉积从靶发射的导电材料的粒子，形成薄膜，同时通过反射溅射气体分子溅射蚀刻薄膜，反射溅射气体分子并且具有高能量。

公开(公告)号：US06699789B2

公开(公告)日：2004-03-02

申请号：US10113705

申请日：2002-03-27

Applicant: Zhih-Sheng Yang ,  Chung-Yan Cheng ,  Ying-Yan Huang ,  Jason C. S. Chu

Inventor： Zhih-Sheng Yang ,  Chung-Yan Cheng ,  Ying-Yan Huang ,  Jason C. S. Chu

IPC: H01L21443

CPC classification number: H01L21/7685 ,  H01L21/2855 ,  H01L21/32051

Abstract: Embodiments of the present invention are directed to a metallization process for reducing the stress existing between the Al—Cu layer and the titanium nitride (TiN) layer, and solving the galvanic problem. The process does so by cooling the wafer in the vacuum apparatus where the metallization process is performed after formation of the Al—Cu layer and before the formation of the TiN layer. In accordance with an aspect of the present invention, a metallization process comprises placing a wafer in an Al—Cu sputtering chamber to form an Al—Cu layer on the wafer, and transferring the wafer to a titanium nitride sputtering chamber. An inert gas is introduced into the titanium nitride sputtering chamber to cool the wafer. A titanium nitride layer is formed on the Al—Cu layer of the wafer in the titanium nitride sputtering layer after cooling the wafer.

Abstract translation: 本发明的实施例涉及一种用于减少存在于Al-Cu层和氮化钛（TiN）层之间的应力并且解决电偶问题的金属化方法。 该方法通过冷却在形成Al-Cu层之后和形成TiN层之前进行金属化处理的真空装置中的晶片。 根据本发明的一个方面，金属化工艺包括将晶片放置在Al-Cu溅射室中以在晶片上形成Al-Cu层，并将晶片转移到氮化钛溅射室。 将惰性气体引入到氮化钛溅射室中以冷却晶片。 在冷却晶片之后，在氮化钛溅射层中的晶片的Al-Cu层上形成氮化钛层。

公开(公告)号：US06699786B2

公开(公告)日：2004-03-02

申请号：US10313290

申请日：2002-12-06

Applicant: Ziyuan Liu

Inventor： Ziyuan Liu

IPC: H01L21443

CPC classification number: H01L21/76838 ,  C23C16/42 ,  C23C16/56 ,  H01L21/28061 ,  H01L21/32053

Abstract: Tungsten silicide WSix is grown through reduction of WF6 with SiCl2H2, and the flow rate between WF6 and SiCl2H2 is controlled in such a manner that the composition ratio x ranges from 2.0 to 2.2 in an initial stage for forming cores on a doped polysilicon layer, and is treated with heat at 700 degrees to 850 degrees in centigrade so as to grow tungsten silicide grains with orientation faster than tungsten silicide grains with orientation; the tungsten silicide WSix is tightly adhered to the doped polysilicon, and the abnormal oxidation is restricted during the heat treatment.

Abstract translation: 钨硅化物WSix通过用SiCl 2 H 2还原WF 6而生长，WF6和SiCl 2 H 2之间的流速以这样一种方式进行控制，即在掺杂多晶硅层上形成芯的初始阶段，组成比x在2.0至2.2范围内，以及 以700摄氏度至850摄氏度的热量进行处理，以便使具有<001>取向的硅化钨晶粒长于具有<101>取向的硅化钨晶粒; 钨硅化物WSix紧密地粘附到掺杂的多晶硅，并且在热处理期间异常氧化受到限制。

公开(公告)号：US06335276B1

公开(公告)日：2002-01-01

申请号：US09417045

申请日：1999-10-12

Applicant: Woon-Yong Park ,  Bum-Ki Baek

Inventor： Woon-Yong Park ,  Bum-Ki Baek

IPC: H01L21443

CPC classification number: H01L27/1288 ,  G02F1/13458 ,  G02F1/136204 ,  G02F1/136227 ,  G02F2001/136236 ,  H01L27/1214

Abstract: A gate wire including a plurality of gate lines and gate electrodes in the display area, and gate pads in the peripheral area is formed on a substrate having a display area and a peripheral area. A gate insulating layer, a semiconductor layer, an ohmic contact layer and a conductor layer are sequentially deposited, and the conductor layer and the ohmic contact are patterned to form a data wire including a plurality of data lines, a source electrode and a drain electrode of the display area and data pads of the peripheral area, and an ohmic contact layer pattern thereunder. A passivation layer is deposited and a positive photoresist layer is coated thereon. The photoresist layer is exposed to light through one or more masks having different transmittance between the display area and the peripheral area. The photoresist layer is developed to form a photoresist pattern having the thickness that varies depending on the position. At this time, a thin portion and a thick portion of the photoresist pattern are provided for the display area, and a thick portion and a zero thickness portion for the peripheral area. In the peripheral area, the portions of the passivation layer, the semiconductor layer and the gate insulating layer on the gate pads, and the portions of the passivation layer on the data pads, under the zero thickness portion, are removed. In the display area, the thin portion of the photoresist pattern, and the portions of the passivation layer and the semiconductor layer thereunder are removed but the portions of the passivation layer under the thick portions of the photoresist pattern is not removed. Then, a plurality of pixel electrodes, redundant gate pads and redundant data pads are formed.

Abstract translation: 在具有显示区域和周边区域的基板上形成包括显示区域中的多个栅极线和栅电极的栅极线以及周边区域中的栅极焊盘。 依次沉积栅极绝缘层，半导体层，欧姆接触层和导体层，并且对导体层和欧姆接触进行图案化以形成包括多条数据线，源电极和漏电极的数据线 的周边区域的显示区域和数据焊盘以及其下的欧姆接触层图案。 沉积钝化层，并在其上涂覆正性光致抗蚀剂层。 光致抗蚀剂层通过在显示区域和周边区域之间具有不同透射率的一个或多个掩模曝光。 光致抗蚀剂层被显影以形成具有根据位置而变化的厚度的光致抗蚀剂图案。 此时，为显示区域设置有光致抗蚀剂图形的薄部分和厚部分，并且为周边区域设置厚部分和零厚度部分。 在外围区域中，除去栅极焊盘上的钝化层，半导体层和栅极绝缘层的部分以及零厚度部分下的数据焊盘上的钝化层的部分。 在显示区域中，去除了光致抗蚀剂图案的薄部分以及钝化层和其下面的半导体层的部分，但是未除去光致抗蚀剂图案的厚部下方的钝化层的部分。 然后，形成多个像素电极，冗余栅极焊盘和冗余数据焊盘。

公开(公告)号：US06797613B2

公开(公告)日：2004-09-28

申请号：US10196698

申请日：2002-07-16

Applicant: Bernhard Sell ,  Annette Sänger ,  Georg Schulze-Icking

Inventor： Bernhard Sell ,  Annette Sänger ,  Georg Schulze-Icking

IPC: H01L21443

CPC classification number: H01L21/28556 ,  H01L21/28518

Abstract: Tungsten silicide layers are formed on a substrate and a semiconductor component has deep trench capacitors with a filling of tungsten silicide. The tungsten silicide layers are deposited on the substrate at a temperature of less than 400° C. and at a pressure of less than 10 torr from the vapor phase. The vapor phase hs a tungsten-containing precursor substance and a silicon-containing precursor substance. The molar ratio of the silicon-containing precursor compound to the tungsten-containing precursor compound in the vapor phase is selected to be greater than 500.

Abstract translation: 在衬底上形成硅化钨层，并且半导体部件具有填充硅化钨的深沟槽电容器。 硅化钨层在低于400℃的温度和低于10托的压力下沉积在基底上。 气相hs是含钨前体物质和含硅前体物质。 气相中含硅前体化合物与含钨前体化合物的摩尔比选择为大于500。