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    Acquisition process by analog signal sampling, and an acquisition system to implement such a process
    2.
    发明授权
    Acquisition process by analog signal sampling, and an acquisition system to implement such a process 失效
    采集过程采用模拟信号采样，采集系统实现这一过程

    公开(公告)号：US06667894B2

    公开(公告)日：2003-12-23

    申请号：US10022839

    申请日：2001-12-20

    Applicant: Daniel Arnoux ,  Claude Genter ,  Francisque Pion

    Inventor： Daniel Arnoux ,  Claude Genter ,  Francisque Pion

    IPC: G11C2700

    CPC classification number: G11C8/04 ,  G11C27/02 ,  G11C27/024

    Abstract: An acquisition process for signal sampling includes high-speed analog signal sampling, storing the samples of the analog signal in a matrix of memory cells, and re-reading the samples from the cells at low speed. Two identical memory devices are provided in each memory cell. One sample of an analog signal is stored in one memory device, and one sample of that signal that is out of phase is stored in the other memory device.

    Abstract translation: 用于信号采样的采集过程包括高速模拟信号采样，将模拟信号的样本存储在存储器单元的矩阵中，并且以低速从单元重新读取采样。 在每个存储单元中提供两个相同的存储器件。 模拟信号的一个采样被存储在一个存储器件中，并且异相的该信号的一个采样被存储在另一个存储器件中。

    Structure and method for correction of defective analog data in a nonvolatile semiconductor memory
    3.
    发明授权
    Structure and method for correction of defective analog data in a nonvolatile semiconductor memory 有权
    用于校正非易失性半导体存储器中的有缺陷的模拟数据的结构和方法

    公开(公告)号：US06445602B1

    公开(公告)日：2002-09-03

    申请号：US09427838

    申请日：1999-10-26

    Applicant: Shingo Kokudo ,  Youichi Nakasone ,  Fumitaka Okamoto

    Inventor： Shingo Kokudo ,  Youichi Nakasone ,  Fumitaka Okamoto

    IPC: G11C2700

    CPC classification number: G11C27/005 ,  G11C27/00

    Abstract: A nonvolatile semiconductor memory includes a memory unit, memory control unit, defect position detection unit, and data correction unit. The memory unit has a plurality of memory cells to discretely store an analog signal such as an image signal as analog data in the form of an analog value. The memory control unit sequentially selects the memory cells as a read out target of the memory unit in response to a predetermined clock. The defect position detection unit detects, on the basis of defect position information indicating a position of defective analog data included in the analog data read out from the memory unit, whether a memory cell corresponding to the defect position is selected by the memory control unit, and outputs a detection output. The data correction unit corrects the analog data at the defect position in accordance with the detection output from the defect position detection unit by using another analog data of the analog signal stored in said memory unit.

    Abstract translation: 非易失性半导体存储器包括存储单元，存储器控制单元，缺陷位置检测单元和数据校正单元。 存储单元具有多个存储器单元，以模拟值的形式离散地存储诸如图像信号的模拟信号作为模拟数据。 存储器控制单元响应于预定时钟顺序选择存储单元作为存储单元的读出目标。 缺陷位置检测单元基于指示从存储单元读出的模拟数据中包含的缺陷模拟数据的位置的缺陷位置信息，检测由存储器控制单元是否选择与缺陷位置对应的存储单元， 并输出检测输出。 数据校正单元通过使用存储在所述存储单元中的模拟信号的另一个模拟数据，根据来自缺陷位置检测单元的检测输出，在缺陷位置校正模拟数据。

    Multiple level RAM device
    4.
    发明授权
    Multiple level RAM device 有权

    公开(公告)号：US06801445B2

    公开(公告)日：2004-10-05

    申请号：US10305051

    申请日：2002-11-26

    Applicant: Horst Kn{overscore (o)}dgen

    Inventor： Horst Kn{overscore (o)}dgen

    IPC: G11C2700

    CPC classification number: G11C7/16 ,  G11C11/565

    Abstract: A multiple level logic memory device is achieved. The device comprises, first, a plurality of memory cells capable of storing an analog voltage. Second, there is included a means of converting an external data word value comprising one value of a set of at least three possible values into a writing analog voltage corresponding to the external data word value. Third, a means of decoding an external address value in response to a write command such that the writing analog voltage is electrically coupled to the memory cell is included. Fourth, there is included a means of converting the memory cell analog voltage into an external data word value comprising one value of the set of at least three possible values corresponding to the memory cell analog voltage. Finally, a means of encoding the external address value in response to a read command such that the memory cell analog voltage is electrically coupled to the means of converting the memory cell analog voltage is used.

    Recording system, data recording device, memory device, and data recording method
    6.
    发明授权
    Recording system, data recording device, memory device, and data recording method 有权
    记录系统，数据记录装置，存储装置和数据记录方法

    公开(公告)号：US06388908B1

    公开(公告)日：2002-05-14

    申请号：US09806133

    申请日：2001-03-26

    Applicant: Shigeo Araki ,  Kenichi Nakanishi

    Inventor： Shigeo Araki ,  Kenichi Nakanishi

    IPC: G11C2700

    CPC classification number: G06F3/0613 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/0607 ,  G06F2212/2022 ,  G11C7/16 ,  G11C7/22 ,  G11C8/12 ,  G11C2207/16

    Abstract: Data 30 is recorded into storages 0 to 3 in parallel. Writing sectors are selected from a plurality of clusters so that the sectors are continuously arranged in each cluster, and the data is simultaneously written into the selected sectors. In the case where the sectors numbered in the original order are written into the storages 0 to 3 in parallel, the data of No. 0 is recorded into the head sector in the cluster of the storage 0, the data of No. 16 is recorded into the head sector in the cluster of the storage 1, the data of No. 32 is recorded into the head sector in the cluster of the storage 2, and the data of No. 48 is recorded into the head sector in the cluster of the storage 3, respectively. Thus, the data is arranged in the original order into the cluster constructed in the same storage. When the data is written into a plurality of storages in parallel, the compatibility of the file format of the written data is held.

    Abstract translation: 数据30被并行地记录到存储器0到3中。 从多个簇中选择写入扇区，使得扇区被连续排列在每个簇中，并且数据被同时写入所选择的扇区。 在以原始顺序编号的扇区并行地写入存储器0至3的情况下，将0号的数据记录在存储器0的簇中的头扇区中，记录16号的数据 将32号的数据记录在存储器2的簇中的头扇区中，并将48号的数据记录在存储器2的簇中的头扇区中 存储3个。 因此，数据以原始顺序排列到同一存储器中构建的群集中。 当数据被并行写入多个存储器时，保持写入数据的文件格式的兼容性。

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