公开(公告)号：US20020176272A1

公开(公告)日：2002-11-28

申请号：US09863730

申请日：2001-05-23

Applicant: International Business Machines Corporation

Inventor： John Kenneth DeBrosse ,  William Robert Reohr

IPC: G11C017/02

CPC classification number: G11C8/12 ,  G11C11/15

Abstract: A magnetic memory device for selectively writing one or more memory cells in the memory device includes a plurality of global write lines for selectively conveying a destabilizing current, the global write lines being disposed from the memory cells such that the destabilizing current passing through the global write lines does not destabilize unselected memory cells in the memory device, each global write line including a plurality of segmented write lines operatively connected thereto. The memory device further includes a plurality of segmented groups, each segmented group including a plurality of memory cells operatively coupled to a corresponding segmented write line, each segmented write line being disposed in relation to the plurality of corresponding memory cells such that the destabilizing current passing through the segmented write line destabilizes the corresponding memory cells for writing. A plurality of segmented group select switches, each group select switch being operatively connected between a corresponding segmented write line and a global write line, includes a group select input for receiving a group select signal, the group select switch completing an electrical circuit between the corresponding segmented write line and the global write line in response to the group select signal. The memory device further includes a plurality of bit lines operatively coupled to each of the memory cells for selectively writing the state of the memory cells.

Abstract translation: 用于选择性地将一个或多个存储器单元写入存储器件的磁存储器件包括多个全局写入线，用于选择性地传送不稳定电流，全局写入线从存储器单元布置，使得通过全局写入的不稳定电流 线不会使存储器件中未选择的存储器单元不稳定，每个全局写入行包括与其可操作地连接的多个分段写入线。 存储器件还包括多个分段组，每个分段组包括可操作地耦合到对应的分段写入线的多个存储单元，每个分段写入线相对于多个对应的存储单元设置，使得不稳定电流通过 通过分段写入线使相应的存储单元不稳定写入。 多个分组组选择开关，每个分组选择开关可操作地连接在对应的分段写入线和全局写入线之间，包括用于接收组选择信号的组选择输入，组选择开关完成对应的 分段写入行和全局写入行响应组选择信号。 存储器件还包括可操作地耦合到每个存储器单元的多个位线，用于选择性地写存储器单元的状态。

公开(公告)号：US20030137864A1

公开(公告)日：2003-07-24

申请号：US10055299

申请日：2002-01-23

Inventor： Anthony Holden ,  Frederick A. Perner

IPC: G11C017/02

CPC classification number: G11C11/15

Abstract: A system and method for determining the logic state of a memory cell in a magnetic tunnel junction (MTJ) memory device based on the ratio of the current through the cell at different bias points are disclosed. A memory cell in an MJT memory device is sequentially subjected to at least two different bias voltages. The current through the cell at each of the bias voltages is measured, and a ratio of the different currents is determined. The ratio is then compared with a predetermined value to determine the logic state of the cell. The predetermined value can be a known value. Alternatively, the predetermined value can be determined by application of the system and method to a reference cell having a known logic state.

公开(公告)号：US20020054500A1

公开(公告)日：2002-05-09

申请号：US09985770

申请日：2001-11-06

Applicant: SANYO ELECTRIC CO., LTD.

Inventor： Kouichi Yamada

IPC: G11C017/02

CPC classification number: H01L27/228 ,  G11C11/16

Abstract: A magnetic memory device capable of preventing complication of the structure of an amplifier (sense amplifier) and enabling high-speed reading is provided. In this magnetic memory device, a memory cell is formed by a pair of first and second storage elements exhibiting a ferromagnetic tunnel effect and a pair of first and second transistors while an amplifier detects potential difference between a bit line and an inverted bit line connected to the pair of first and second storage elements. Thus, data can be readily read. Further, the value of a small current flowing to the bit line may not be detected dissimilarly to a case of forming the memory cell by a storage element exhibiting a ferromagnetic tunnel effect and a transistor. Consequently, the structure of the amplifier is not complicated. Further, no amplifier having a complicated structure may be employed, whereby high-speed reading is enabled.

Abstract translation: 提供了能够防止放大器（感测放大器）的结构的复杂化并且实现高速读取的磁存储器件。 在这种磁存储器件中，存储单元由具有铁磁隧道效应的一对第一和第二存储元件以及一对第一和第二晶体管形成，而放大器检测位线和连接到 一对第一和第二存储元件。 因此，可以容易地读取数据。 此外，流过位线的小电流的值可能不与由具有铁磁隧道效应的存储元件和晶体管形成存储单元的情况不同。 因此，放大器的结构并不复杂。 此外，不能使用具有复杂结构的放大器，从而能够进行高速读取。

公开(公告)号：US20020159285A1

公开(公告)日：2002-10-31

申请号：US09959591

申请日：2002-01-25

Inventor： Stephen Morley ,  Kevin Lloyd-Jones ,  Dominic P. McCarthy ,  Peter Joseph Bramhall

IPC: G11C017/02

CPC classification number: G11C7/1006 ,  G11C11/16

Abstract: A data storage device comprises at least one array of memory elements arranged in a plurality of rows and columns; coding means for coding an input data into a form having a balanced proportion of null1nulls and null0nulls, said coding means comprising means for applying an output of a pseudo random bit sequence generator to said incoming data, wherein the coded data is stored in the array of memory elements such that the null1nulls and null0nulls are spatially distributed relatively evenly across the plurality of memory elements; and decoding means for decoding the coded data read from the plurality of memory elements, into the original data.

Abstract translation: 数据存储装置包括以多行和列排列的至少一组存储元件阵列; 编码装置，用于将输入数据编码成具有平衡比例为“1”和“0”的形式，所述编码装置包括用于将伪随机比特序列发生器的输出应用于所述输入数据的装置，其中编码数据被存储在 存储器元件的阵列，使得“1”和“0”在多个存储器元件中相对均匀地空间分布; 以及用于将从多个存储元件读取的编码数据解码为原始数据的解码装置。

公开(公告)号：US20020105823A1

公开(公告)日：2002-08-08

申请号：US09990321

申请日：2001-11-23

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE

Inventor： Olivier Redon ,  Bernard Dieny ,  Bernard Rodmacq

IPC: G11C017/02

CPC classification number: H01L27/226 ,  B82Y10/00 ,  B82Y25/00 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3268 ,  H01F10/3286 ,  H01L43/08

Abstract: Magnetic spin polarising and magnetisation rotation device with memory and writing process, using such a device. According to the invention, the device includes a means of polarising the spin of electrons, which consists of a magnetic layer (20) whose magnetisation is perpendicular to the plane of magnetisation of the respective anchored (12) and free (16) layers. The magnetisation in the free layer (16) then rotates within a plane, which is either the plane of the layer, or a perpendicular plane. Application in the manufacture of magnetic memories.

Abstract translation: 磁旋转极化和磁化旋转装置具有记忆和写入过程，采用这种器件。 根据本发明，该器件包括使电子自旋偏振的装置，其由磁化垂直于相应锚定（12）和自由（16）层的磁化平面的磁性层（20）组成。 然后，自由层（16）中的磁化在平面内旋转，该平面是层的平面或垂直平面。 应用于制造磁记忆体。

公开(公告)号：US20010026466A1

公开(公告)日：2001-10-04

申请号：US09803571

申请日：2001-03-09

Applicant: Matsushita Electric Industrial Co. Ltd.

Inventor： Hideaki Adachi ,  Akihiro Odagawa ,  Masayoshi Hiramoto ,  Nozomu Matsukawa ,  Hiroshi Sakakima

IPC: G11C017/02

CPC classification number: G11C11/16

Abstract: A magnetic control device including an antiferromagnetic layer, a magnetic layer placed in contact with one side of the antiferromagnetic layer, and an electrode placed in contact with another side of the antiferromagnetic layer, wherein the direction of the magnetization of the magnetic layer is controlled by voltage applied between the magnetic layer and the electrode. In particular, when an additional magnetic layer is further laminated on the magnetic layer placed in contact with the antiferromagnetic layer via a non-magnetic layer, the direction of the magnetization of the controlled magnetic layer can be detected as a change in the electric resistance. Since such a magnetic control device, in principle, responds to the electric field or magnetic field, it forms a magnetic component capable of detecting an electric signal or a magnetic signal. In this case, the direction of the magnetization basically is maintained until the next signal is detected, so that such a device also can form an apparatus. Thus, a magnetic control device capable of controlling the magnetization with voltage and magnetic component and a memory apparatus using the same are provided.

Abstract translation: 一种磁控制装置，包括反铁磁层，与反铁磁层的一侧接触的磁性层和与反铁磁性层的另一侧接触的电极，其中磁性层的磁化方向由 施加在磁性层和电极之间的电压。 特别地，当通过非磁性层进一步层叠在与反铁磁性层接触的磁性层上的附加磁性层时，可以检测受控磁性层的磁化方向作为电阻的变化。 由于这种磁性控制装置原则上对电场或磁场进行响应，所以形成能够检测电信号或磁信号的磁性部件。 在这种情况下，磁化的方向基本上被维持直到检测到下一个信号，使得这样的装置也可以形成装置。 因此，提供了能够用电压和磁性成分控制磁化的磁控制装置和使用该磁控制装置的存储装置。

公开(公告)号：US20040109339A1

公开(公告)日：2004-06-10

申请号：US10459133

申请日：2003-06-11

Inventor： David Tsang

IPC: G11C017/02

CPC classification number: G11C11/16

Abstract: A method and system for providing and using a magnetic random access memory are disclosed. The method and system include providing a plurality of magnetic memory cells, a first plurality of write lines, and a second plurality of write lines. The first plurality of write lines is a plurality of magnetic write lines. At least one of the plurality of magnetic lines and at least one of the second plurality of write lines each carrying a current for writing to at least one of the plurality of magnetic memory cells. Preferably, the plurality of magnetic write lines have soft magnetic properties and are preferably magnetic bit lines. For magnetic tunneling junction stacks within the magnetic memory cells, the magnetic bit lines are preferably significantly thicker than and closely spaced to the free layers of the magnetic memory cells.

Abstract translation: 公开了一种用于提供和使用磁随机存取存储器的方法和系统。 该方法和系统包括提供多个磁存储器单元，第一多个写入线和第二多个写入线。 第一组写入线是多条磁写入线。 多个磁线中的至少一个和第二多个写入线中的至少一个写入线各自承载用于向多个磁存储单元中的至少一个写入的电流。 优选地，多个磁写入线具有软磁性质，并且优选地是磁位线。 对于磁存储器单元内的磁隧道结叠层，磁位线优选地明显地比磁存储单元的自由层更厚并且紧密地间隔开。

公开(公告)号：US20020145902A1

公开(公告)日：2002-10-10

申请号：US09989155

申请日：2001-11-21

Applicant: Mitsubishi Denki Kabushiki Kaisha

Inventor： Tatsuya Kunikiyo ,  Katsumi Eikyu ,  Shigenobu Maeda

IPC: G11C017/02

CPC classification number: B82Y10/00 ,  G11C11/15 ,  G11C11/16 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01025 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A plurality of word lines (WL1) are provided in parallel to one another and a plurality of bit lines (BL1) are provided in parallel to one another, intersecting the word lines (WL1) thereabove. MRAM cells (MC2) are formed at intersections of the word lines and the bit lines therebetween. MRAM cells (MC3) are provided so that an easy axis indicated by the arrow has an angle of 45 degrees with respect to the bit lines and the word lines. Thus, an MRAM capable of cutting the power consumption in writing is achieved and further an MRAM capable of reducing the time required for erasing and writing operations is achieved.

Abstract translation: 多个字线（WL1）彼此并联设置，并且多个位线（BL1）彼此平行地设置，与上述字线（WL1）相交。 在字线和它们之间的位线的交点处形成MRAM单元（MC2）。 提供MRAM单元（MC3），使得由箭头表示的容易轴相对于位线和字线具有45度的角度。 因此，实现了能够切换写入功耗的MRAM，并且进一步实现了能够减少擦除和写入操作所需的时间的MRAM。

公开(公告)号：US20020097599A1

公开(公告)日：2002-07-25

申请号：US10033320

申请日：2001-12-27

Inventor： Chang Yong Kang ,  Chang-Shuk Kim

IPC: G11C017/02

CPC classification number: H01L27/228 ,  B82Y10/00 ,  G11C11/16

Abstract: A magnetic random access memory (MRAM) is disclosed. In order to achieve high integration, the MRAM includes a word line formed in an active region of a semiconductor substrate, and used as a read line and a write line; a ground line and a lower read layer positioned on opposite sides of the active region of the semiconductor substrate; a seed layer contacting the lower read layer, and being overlapped with the upper portion of the word line; an MTJ cell contacting the upper portion of the seed layer at the upper portion of the word line; and a bit line contacting the MTJ cell, and crossing the word line in a vertical direction.

Abstract translation: 公开了一种磁性随机存取存储器（MRAM）。 为了实现高集成度，MRAM包括形成在半导体衬底的有源区中并被用作读取线和写入线的字线; 位于所述半导体衬底的有源区的相对侧上的接地线和下读取层; 与下部读取层接触并与字线的上部重叠的种子层; MTJ单元在字线的上部与种子层的上部接触; 以及与MTJ单元接触的位线，并且在垂直方向上与字线交叉。

公开(公告)号：US20020097597A1

公开(公告)日：2002-07-25

申请号：US09965086

申请日：2001-09-27

Applicant: Infineon Technologies North America Corp.

Inventor： Hans-Heinrich Viehmann

IPC: G11C017/02

CPC classification number: G11C7/12 ,  G11C7/18 ,  G11C8/08 ,  G11C8/14 ,  G11C11/16

Abstract: A memory device comprising a plurality of bit lines and a plurality of word lines forming a cross-point array. A memory cell is located at each of the cross-points in the array. A bit decoder and word decoder are coupled to the bit lines and word lines, respectively. A first series of switch circuits are coupled to and located along the adjacent bit lines resulting in the array being divided into segments along the adjacent bit lines such that a shortened programming current path is provided which results in decreased resistance across the device.

Abstract translation: 一种包括多个位线和形成交叉点阵列的多个字线的存储器件。 存储单元位于阵列中的每个交叉点。 位解码器和字解码器分别耦合到位线和字线。 第一系列开关电路耦合到相邻位线并沿着相邻位线定位，导致阵列沿着相邻位线被分成多个段，使得提供缩短的编程电流路径，这导致跨越器件的电阻降低。