公开(公告)号：US06829664B2

公开(公告)日：2004-12-07

申请号：US10323763

申请日：2002-12-20

Applicant: Tomohiro Nomizo ,  Shoichi Akaiwa ,  Toru Karasawa

Inventor： Tomohiro Nomizo ,  Shoichi Akaiwa ,  Toru Karasawa

IPC: G06F1312

CPC classification number: G06F3/033

Abstract: A controller and a plurality of projectors are connected in a mutually communication enabled state by a network, etc., and thus projection information and control information are sent from the control unit to each of the projectors simultaneously or individually. Also, the control unit obtains operation information, etc. of each of the projectors, and monitors the projectors.

Abstract translation: 控制器和多个投影仪通过网络等相互通信使能状态连接，从而投影信息和控制信息从控制单元同时或单独地发送到每个投影仪。 此外，控制单元获得每个投影仪的操作信息等，并监视投影仪。

公开(公告)号：US06799231B2

公开(公告)日：2004-09-28

申请号：US10274884

申请日：2002-10-22

Applicant: Ching-Ju Hsin ,  Kwang-Lay Chen ,  Po-Cheng Huang ,  Pao-Hsuan Tseng ,  Ming-Chun Su ,  Tsung-Mong Shen

Inventor： Ching-Ju Hsin ,  Kwang-Lay Chen ,  Po-Cheng Huang ,  Pao-Hsuan Tseng ,  Ming-Chun Su ,  Tsung-Mong Shen

IPC: G06F1312

CPC classification number: G06F13/4217

Abstract: The invention relates to a virtual I/O device coupled to a memory controller in a microprocessor of computer, the virtual I/O device and a memory unit being in communication with the memory controller via a common interface so that any of a plurality of peripherals is capable of coupling to an arithmetic and logic unit (ALU) in the microprocessor via the virtual I/O device and the memory controller sequentially, and an excessive time spent on a processing of request and acknowledgement in handshake while packets being received or transmitted between a conventional I/O device and the I/O interface in the microprocessor is significantly reduced.

Abstract translation: 本发明涉及耦合到计算机的微处理器中的存储器控​​制器的虚拟I / O设备，虚拟I / O设备和存储器单元通过公共接口与存储器控制器通信，使得多个外设 能够经由虚拟I / O设备和存储器控制器顺序地耦合到微处理器中的算术和逻辑单元（ALU），并且在握手中的请求和确认处理时花费的时间过长，而分组在 传统的I / O设备和微处理器中的I / O接口显着减少。

公开(公告)号：US06795880B2

公开(公告)日：2004-09-21

申请号：US10288266

申请日：2002-11-05

Applicant: Baofeng Jiang

Inventor： Baofeng Jiang

IPC: G06F1312

CPC classification number: G06F13/4027

Abstract: The present invention relates generally to a method and system for processing data. In a particular embodiment, the method includes receiving data to be processed from a network communication channel, storing the received data to be processed in memory based files at a computer memory that is local to and directly coupled to a processor via a high-speed memory bus, processing the received and stored data at the processor to produce processed data, compressing the processed data using a data compression software routine resident at the computer memory to produced processed and compressed data, and storing the processed and compressed data at a computer disk storage unit.

公开(公告)号：US06732204B2

公开(公告)日：2004-05-04

申请号：US09805029

申请日：2001-03-14

Applicant: Takuya Ishida

Inventor： Takuya Ishida

IPC: G06F1312

CPC classification number: G06F13/4059

Abstract: The objective is to provide a data transfer control device and electronic equipment that implement bit insertion, encoding, decoding, and bit deletion at a slow clock frequency. A bit stuffing circuit and NRZI encoder are provided in a stage before a parallel-serial conversion circuit on the transmission side and an NRZI decoder and a bit unstuffing circuit are provided in a stage after a serial-parallel conversion circuit on the reception side, so that bit stuffing, NRZI encoding, NRZI decoding, and bit unstuffing are implemented on parallel data, not serial data. Any bits that have overflowed due to the bit insertion are carried forward to data for the next clock cycle and any deficiency of bits caused by bit deletion is moved up from the data of the next clock cycle. Insertion (or deletion) of bits is based on the thus calculated bit stuffing (or bit unstuffing) position and the range of parallel data to be output is based on the accumulated total of the number of bits that overflow (or contract).

Abstract translation: 目的是提供一种以慢时钟频率实现位插入，编码，解码和位删除的数据传输控制设备和电子设备。 在发送侧的并行 - 串行转换电路之前的一个阶段提供位填充电路和NRZI编码器，并且在接收侧的串行 - 并行转换电路之后的级中提供NRZI解码器和位不充电电路，因此 该位填充，NRZI编码，NRZI解码和位解混合在并行数据而不是串行数据上实现。 由于位插入而溢出的任何位被转发到下一个时钟周期的数据，并且由位删除引起的位的任何不足都从下一个时钟周期的数据向上移动。 位的插入（或删除）基于这样计算的位填充（或位不填充）位置，并且要输出的并行数据的范围基于累积（或收缩）的位数的累积总数。

公开(公告)号：US06725288B2

公开(公告)日：2004-04-20

申请号：US10084581

申请日：2002-02-27

Applicant: Yoshiyuki Nagao ,  Masanori Kadowaki ,  Masayuki Masuda

Inventor： Yoshiyuki Nagao ,  Masanori Kadowaki ,  Masayuki Masuda

IPC: G06F1312

CPC classification number: G06F13/128 ,  G06F9/4411 ,  G06F12/0646

Abstract: A controller contains an I/O memory and uses a device detecting service to detect a device connected to it through a network and to obtain its device identifying data. A memory map setting service sets a device data area on the I/O memory according to the obtained device identifying data for exchanging data with the connected device and produces a memory map correlating the device data area with a variable data area on the I/O memory correlated to the device. The controller also includes a cyclic service and a data transmission service. The cyclic service transmits and receives data to and from the device periodically in the data linking format according to the memory map and by using the device data area on the I/O memory. The data transmission service transmits the data between the variable data area and the device data area.

Abstract translation: 控制器包含I / O存储器，并使用设备检测服务通过网络检测与其连接的设备，并获得其设备识别数据。 存储器映射设置服务根据所获得的设备识别数据来设置I / O存储器上的设备数据区域，以便与连接的设备交换数据，并产生将设备数据区域与I / O上的可变数据区域相关联的存储器映射 存储器与设备相关。 控制器还包括循环服务和数据传输服务。 循环服务根据存储器映射以及使用I / O存储器上的设备数据区域以数据链接格式周期性地向设备发送数据和从设备接收数据。 数据传输服务在可变数据区和设备数据区之间传送数据。

公开(公告)号：US06697890B1

公开(公告)日：2004-02-24

申请号：US10034878

申请日：2001-12-27

Applicant: Dale E. Gulick ,  Larry D. Hewitt

Inventor： Dale E. Gulick ,  Larry D. Hewitt

IPC: G06F1312

CPC classification number: G06F13/4247 ,  G06F13/4004

Abstract: An I/O node for a computer system including an integrated I/O interface. An input/output node for a computer system that is implemented upon an integrated circuit includes a first transceiver unit, a second transceiver unit, a packet tunnel, a bridge unit and an I/O interface unit. The first transceiver unit may receive and transmit packet transactions on a first link of a packet bus. The second transceiver unit may receive and transmit packet transactions on a second link of the packet bus. The packet tunnel may convey selected packet transactions between the first and second transceiver units. The bridge unit may receive particular packet transactions from the first transceiver may transmit transactions corresponding to the particular packet transactions upon a peripheral bus. The I/O interface unit may receive additional packet transactions from the first transceiver unit and may transmit transactions corresponding to the additional packet transactions upon an I/O link.

Abstract translation: 一个包含集成I / O接口的计算机系统的I / O节点。 在集成电路上实现的用于计算机系统的输入/输出节点包括第一收发器单元，第二收发器单元，分组隧道，桥接单元和I / O接口单元。 第一收发器单元可以在分组总线的第一链路上接收和发送分组事务。 第二收发器单元可以在分组总线的第二链路上接收和发送分组事务。 分组隧道可以在第一和第二收发器单元之间传送所选择的分组事务。 桥接单元可以接收来自第一收发器的特定分组事务可以在外围总线上发送与特定分组事务相对应的事务。 I / O接口单元可以从第一收发器单元接收附加分组事务，并且可以在I / O链路上传送与附加分组事务相对应的事务。

公开(公告)号：US06684275B1

公开(公告)日：2004-01-27

申请号：US09427669

申请日：1999-10-23

Applicant: Jason A. Goldstein

Inventor： Jason A. Goldstein

IPC: G06F1312

CPC classification number: G11C7/1006 ,  G11C2207/107 ,  H03M9/00

Abstract: A serial-to-parallel/parallel-to-serial conversion engine provides a bi-directional interface between a serial TDM highway and a parallel TDM highway. The conversion engine includes a serial-to-parallel data conversion device receives a serially received data word and provides a parallel output data word. The conversion engine includes a serial data input interface that receives the serially received data word and provides a received data word. A serial-to-parallel mapping circuit receives the received data word and generates memory write control and write address signals. A memory device includes a first port responsive to the memory write control signals and write address signals for writing the received data word into the memory device, and a second port responsive to memory read control and read address signals for reading data from the memory device. Output interface circuitry generates the memory read control and read address signals, and receives output data from the memory device and reorders the bits of the parallel output data to provide the parallel data word. The conversion engine also includes a parallel-to-serial conversion device that receives a parallel received data word and provides a serial data word. The parallel-to-serial conversion device includes a memory device having a first port responsive to memory write control and write address signals, and a second port responsive to memory read control and read address signals. A parallel-to-serial mapping circuit receives the parallel received data word and generates the memory write control and write address signals to write a bit shuffled version of the parallel received data word into the memory device. A data output interface generates the memory read control and read address signals to perform reads from the memory device and receives output data from the memory device to provide the serial data word.

Abstract translation: 串行到并行/并行到串行转换引擎在串行TDM高速公路和并行TDM高速公路之间提供双向接口。 该转换引擎包括串并转数据转换装置接收串行接收的数据字并提供并行输出数据字。 转换引擎包括串行数据输入接口，其接收串行接收的数据字并提供接收到的数据字。 串行到并行映射电路接收接收到的数据字，并产生存储器写入控制和写入地址信号。 存储器件包括响应于存储器写入控制信号的第一端口和用于将接收的数据字写入存储器件的写入地址信号，以及响应于存储器读取控制的读取地址信号和用于从存储器件读取数据的读取地址信号的第二端口。 输出接口电路产生存储器读取控制和读取地址信号，并且从存储器件接收输出数据并且重新排列并行输出数据的位以提供并行数据字。 转换引擎还包括并行到串行转换设备，其接收并行接收的数据字并提供串行数据字。 并行到串行转换设备包括具有响应于存储器写控制和写地址信号的第一端口的存储器件，以及响应于存储器读控制和读地址信号的第二端口。 并行到串行映射电路接收并行接收数据字，并产生存储器写入控制和写入地址信号，以将并行接收数据字的位混洗版本写入存储器件。 数据输出接口产生存储器读取控制和读取地址信号以执行从存储器件的读取并从存储器件接收输出数据以提供串行数据字。

公开(公告)号：US06654831B1

公开(公告)日：2003-11-25

申请号：US09519949

申请日：2000-03-07

Applicant: Noel S. Otterness ,  Joseph G. Skazinski

Inventor： Noel S. Otterness ,  Joseph G. Skazinski

IPC: G06F1312

CPC classification number: G06F3/0658 ,  G06F3/0613 ,  G06F3/0689 ,  G06F11/2089

Abstract: A data storage system includes a pluralierty of controllers in a master/slave N-way controller topology. The master controller is coupled to a host system, and each controller is operatively coupled to one of a plurality of data unit arrays. The plurality of data unit arrays each include a plurality of disk units that are linked together. The linked disk units appear as a continuous logical unit and each data unit array forms a data span, such that the plurality of data unit arrays form N-way data spans. Each controller is adapted to transfer data between the data units and the master controller in response to instructions therefrom based on a data configuration. The data is then transferred between the master controller and the host system. The master controller is adapted to balance I/O requests amongst the plurality of controllers and re-direct an I/O request directed to a failed controller to an active controller. Alternatively, the data storage system 300 includes a plurality of controllers in a peer-to-peer N-way controller topology. Any one active controller is adapted to transfer data between the data units and the host system in response to instructions therefrom and balance I/O requests amongst the plurality of controllers and re-direct an I/O request directed to a failed controller to an active controller. Advantages include automatic copying of the host data to an alternate controller for data protection. In addition, if the spans are setup as a RAID 0+5 or some other similar configuration, the workload is automatically distributed among the various controllers.

Abstract translation: 数据存储系统包括主/从N路控制器拓扑中的多个控制器。 主控制器耦合到主机系统，并且每个控制器可操作地耦合到多个数据单元阵列之一。 多个数据单元阵列各自包括连接在一起的多个盘单元。 链接的磁盘单元表现为连续逻辑单元，并且每个数据单元阵列形成数据跨度，使得多个数据单元阵列形成N路数据跨度。 每个控制器适于基于数据配置响应于其指令在数据单元和主控制器之间传送数据。 然后在主控制器和主机系统之间传输数据。 主控制器适于平衡多个控制器之间的I / O请求，并将指向故障控制器的I / O请求重新定向到主动控制器。 或者，数据存储系统300包括对等N路控制器拓扑中的多个控制器。 任何一个主动控制器适于响应于其指令在数据单元和主机系统之间传送数据，并平衡多个控制器之间的I / O请求，并将指向故障控制器的I / O请求重定向到活动 控制器。 优点包括将主机数据自动复制到备用控制器进行数据保护。 此外，如果跨度设置为RAID 0 + 5或其他类似配置，则工作负载将自动分配到各种控制器之间。

公开(公告)号：US06618774B1

公开(公告)日：2003-09-09

申请号：US09527067

申请日：2000-03-16

Applicant: Adrian Christopher Dickens ,  Nigel Anthony Dickens ,  Philip Edward Hudson

Inventor： Adrian Christopher Dickens ,  Nigel Anthony Dickens ,  Philip Edward Hudson

IPC: G06F1312

CPC classification number: H04N7/108 ,  G06F13/385 ,  G09G5/006 ,  G09G2370/045 ,  H04L5/02 ,  H04N5/60 ,  H04N11/00 ,  H04N17/00

Abstract: A system for transmitting electrical signals between a computer and peripherals along a twisted pair cable. The system includes a computer interface, a peripheral interface and a twisted pair cable in communication between the computer interface and the peripheral interface. Video and audio signals from the computer are transmitted via the twisted pair cable to the peripherals. Peripheral signals can also be communicated between the computer and peripherals via the twisted pair cable.

Abstract translation: 一种用于沿着双绞线电缆在计算机和外围设备之间传输电信号的系统。 该系统包括在计算机接口和外围接口之间通信的计算机接口，外设接口和双绞线电缆。 来自计算机的视频和音频信号通过双绞线传输到外围设备。 外围信号也可以通过双绞线在计算机和外围设备之间通信。

公开(公告)号：US06594716B2

公开(公告)日：2003-07-15

申请号：US09892489

申请日：2001-06-28

Applicant: Siamack Nemazie ,  Kaushik Popat ,  Balaji Virajpet ,  William R. Foland, Jr. ,  Roger McPherson ,  Maoxin Wei ,  Vineet Dujari ,  Shiang-Jyh Chang

Inventor： Siamack Nemazie ,  Kaushik Popat ,  Balaji Virajpet ,  William R. Foland, Jr. ,  Roger McPherson ,  Maoxin Wei ,  Vineet Dujari ,  Shiang-Jyh Chang

IPC: G06F1312

CPC classification number: G06F3/0626 ,  G06F3/0658 ,  G06F3/0673 ,  G06F3/0676 ,  G11B19/00 ,  G11B20/10009 ,  G11B25/043

Abstract: An integrated data storage control system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated system design. The integrated circuit is rendered using a single integrated circuit technology type (e.g., digital CMOS) for all components. Analog and digital circuits are combined in such a way as to eliminate or reduce noise or interference in digital circuits from analog circuit components. Individual elements may have their outputs and inputs MUXed together such that individual elements can be selectively switched (during testing modes) such that the integrated circuit emulates or behaves in the same or similar manner as one of the prior art components. The present invention may be applied to magnetic hard disk drives (HDDs) or other types of storage devices such as floppy disk controllers, optical disk drives (e.g., CD-ROMs and the like), tape drives, and other data storage devices.