公开(公告)号：US6166979A

公开(公告)日：2000-12-26

申请号：US300402

申请日：1999-04-27

Applicant: Junichi Miyamoto

Inventor： Junichi Miyamoto

IPC: G11C11/56 ,  A11C13/00

CPC classification number: G11C16/0483 ,  G11C7/1039 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5621 ,  G11C2211/5641 ,  G11C2211/5642

Abstract: A nonvolatile semiconductor memory device includes nonvolatile memory cells (C), constant voltage circuits for applying one of different verify voltages to control gates of the nonvolatile memory cells C in response to control data introduced into the memory device from the exterior, and writing and sensing circuit circuits for applying a potential to drains of the nonvolatile memory cells C in response to write data introduced into the memory device and for detecting and amplifying currents between drains and sources of the nonvolatile memory cells. By dividing the memory cell array 501 and a serial register 502 into some parts and by connecting an external SRAM 503 so as to progress the transfer of data from the memory cell array 501 to the serial register 502 and the transfer of data from the serial register 502 to the external SRAM 503 in parallel, the read speed is increased.

Abstract translation: 非易失性半导体存储器件包括非易失性存储单元（C），用于响应于从外部引入存储器件的控制数据，将不同验证电压之一施加到非易失性存储单元C的控制栅极的恒压电路，以及写入和检测 电路电路，用于响应于引入到存储器件的写入数据，并且用于检测和放大非易失性存储器单元的漏极和源极之间的电流，向非易失性存储单元C的漏极施加电位。 通过将存储单元阵列501和串行寄存器502分成若干部分并连接外部SRAM 503，以便将数据从存储单元阵列501传送到串行寄存器502并从串行寄存器传送数据 502并联到外部SRAM 503，读取速度增加。

公开(公告)号：US6028808A

公开(公告)日：2000-02-22

申请号：US851862

申请日：1997-05-06

Applicant: Richard G. Cliff ,  L. Todd Cope ,  Cameron R. Mc Clintock ,  William Leong ,  James A. Watson ,  Joseph Huang ,  Bahram Ahanin

Inventor： Richard G. Cliff ,  L. Todd Cope ,  Cameron R. Mc Clintock ,  William Leong ,  James A. Watson ,  Joseph Huang ,  Bahram Ahanin

IPC: G01R31/3185 ,  G11C8/12 ,  H03K19/094 ,  H03K19/173 ,  H03K19/177 ,  A11C13/00

CPC classification number: H03K19/09429 ,  G11C8/12 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/1776 ,  H03K19/1778 ,  H03K19/17792 ,  G01R31/318516

Abstract: A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.