MOCVD and annealing processes for C-axis oriented ferroelectric thin films
    1.
    发明授权
    MOCVD and annealing processes for C-axis oriented ferroelectric thin films 有权
    C轴取向铁电薄膜的MOCVD和退火工艺

    公开(公告)号:US06475813B1

    公开(公告)日:2002-11-05

    申请号:US09929711

    申请日:2001-08-13

    IPC分类号: A01L2100

    摘要: A method of fabricating a c-axis ferroelectric thin film includes preparing a substrate; depositing a layer of ferroelectric material by metal organic chemical vapor deposition, including using a precursor solution having a ferroelectric material concentration of about 0.1 M/L at a vaporizer temperature of between about 140° C. to 200° C.; and annealing the substrate and the ferroelectric material at a temperature between about 500° C. to 560° C. for between about 30 minutes to 120 minutes.

    摘要翻译: 制造c轴铁电薄膜的方法包括:制备基板; 通过金属有机化学气相沉积沉积铁电材料层,包括在蒸发器温度为约140℃至200℃之间使用铁电材料浓度为约0.1M / L的前体溶液; 以及在大约500℃至560℃之间的温度下将所述衬底和所述铁电材料退火约30分钟至120分钟。

    Semiconductor device and method for producing the same
    3.
    发明授权
    Semiconductor device and method for producing the same 失效
    半导体装置及其制造方法

    公开(公告)号:US06682966B2

    公开(公告)日:2004-01-27

    申请号:US10171540

    申请日:2002-06-17

    IPC分类号: A01L2100

    摘要: A semiconductor device according to the present invention includes a semiconductor substrate; device isolation regions provided in the semiconductor substrate; a first conductivity type semiconductor layer provided between the device isolation regions; a gate insulating layer provided on an active region of the first conductivity type semiconductor layer; a gate electrode provided on the gate insulating layer; gate electrode side wall insulating layers provided on side walls of the gate electrode; and second conductivity type semiconductor layers provided adjacent to the gate electrode side wall insulating layers so as to cover a portion of the corresponding device isolation region, the second conductivity type semiconductor layers acting as a source region and/or a drain region. The gate electrode and the first conductivity type semiconductor layer are electrically connected to each other. The second conductivity type semiconductor layers are provided above the first conductivity type semiconductor layer and have a thickness which gradually increases from the device isolation region toward the gate electrode.

    摘要翻译: 根据本发明的半导体器件包括半导体衬底; 设置在半导体衬底中的器件隔离区; 设置在所述器件隔离区之间的第一导电型半导体层; 设置在所述第一导电型半导体层的有源区上的栅极绝缘层; 设置在所述栅极绝缘层上的栅电极; 设置在栅电极的侧壁上的栅电极侧壁绝缘层; 以及与栅电极侧壁绝缘层相邻设置以覆盖对应的器件隔离区的一部分的第二导电类型半导体层,作为源区和/或漏区的第二导电类型半导体层。 栅电极和第一导电类型半导体层彼此电连接。 第二导电类型半导体层设置在第一导电类型半导体层之上,并且具有从器件隔离区朝向栅极电极逐渐增加的厚度。

    Method for manufacturing tapered opening using an anisotropic etch during the formation of a semiconductor device
    4.
    发明授权
    Method for manufacturing tapered opening using an anisotropic etch during the formation of a semiconductor device 有权
    在形成半导体器件期间使用各向异性蚀刻制造锥形开口的方法

    公开(公告)号:US06524875B2

    公开(公告)日:2003-02-25

    申请号:US10015260

    申请日:2001-12-11

    IPC分类号: A01L2100

    CPC分类号: H01L21/76804

    摘要: A method and apparatus for improving the accuracy of a contact to an underlying layer comprises the steps of forming a first photoresist layer over the underlying layer, forming a mask layer over the first photoresist layer, then forming a patterned second photoresist layer over the mask layer. The mask layer is patterned using the second photoresist layer as a pattern then the first photoresist layer is patterned using the mask layer as a pattern. A tapered hole is formed in the first photoresist layer, for example using an anisotropic etch. The tapered hole has a bottom proximate the underlying layer and a top distal the underlying layer with the top of the hole being wider than the bottom of the hole.

    摘要翻译: 用于提高与下层的接触精度的方法和装置包括以下步骤:在下层上形成第一光致抗蚀剂层,在第一光致抗蚀剂层上形成掩模层,然后在掩模层上形成图案化的第二光致抗蚀剂层 。 使用第二光致抗蚀剂层作为图案对掩模层进行图案化,然后使用掩模层作为图案来对第一光致抗蚀剂层进行图案化。 在第一光致抗蚀剂层中形成锥形孔,例如使用各向异性蚀刻。 锥形孔具有靠近下层的底部,并且顶部远离下面的层,孔的顶部比孔的底部更宽。