公开(公告)号：US5594633A

公开(公告)日：1997-01-14

申请号：US514930

申请日：1995-08-14

申请人： Hiroshi Asazawa

发明人： Hiroshi Asazawa

IPC分类号： G06G7/163 ,  H03D7/14 ,  H03F3/45 ,  H03G1/00 ,  H03H11/02 ,  H03H11/22 ,  H03K19/086 ,  H02M7/00

CPC分类号： H03G1/0023 ,  H03D7/1408 ,  H03D7/1433 ,  H03D7/1458 ,  H03D7/1491 ,  H03F3/45071 ,  H03D2200/0033 ,  H03D2200/0084 ,  H03F2203/45098 ,  H03F2203/45476

摘要： A voltage-to-current converting circuit configured to convert an input voltage signal into a pair of complementary current signals by use of a current mirror, comprises a transistor 4 connected in the form of a diode and connected in series with a constant current source 21, a transistor 3 having a collector connector to a collector of the transistor 4, a transistor 2 having a base connected to a base of the transistor 3 so as to form a current mirror in cooperation with the transistor 3, the base of the transistor 2 being connected to receive an input voltage signal Vin, a bias circuit 5 for biasing the base of the transistors 3 and 2, and a transistor 1 having a base connected to a base of the transistor 4 so as to form a current mirror in cooperation with the transistor 4. The input voltage Vin is converted into a collector current I1 of the transistor 1 and a collector current I2 of the transistor 2. Thus, the voltage-to-current converting circuit is composed of only NPN transistors, so that a manufacturing process is simplified. In addition, since no emitter follower is included, a low voltage operation can be realized. This circuit can be applied to a multiplier, frequency doubler, a frequency mixer, etc.

摘要翻译： 配置为通过使用电流镜将输入电压信号转换为一对互补电流信号的电压 - 电流转换电路包括以二极管形式连接并与恒流源21串联连接的晶体管4 晶体管3具有到晶体管4的集电极的集电极连接器，晶体管2具有与晶体管3的基极连接的基极，以便与晶体管3配合形成电流镜，晶体管2的基极 连接以接收输入电压信号Vin，用于偏置晶体管3和2的基极的偏置电路5以及具有连接到晶体管4的基极的基极的晶体管1，以与 晶体管4.输入电压Vin被转换为晶体管1的集电极电流I1和晶体管2的集电极电流I2。因此，电压 - 电流转换电路仅由NPN晶体管 从而简化了制造过程。 此外，由于不包括射极跟随器，因此可以实现低电压操作。 该电路可应用于倍频器，倍频器，混频器等

公开(公告)号：US07483306B2

公开(公告)日：2009-01-27

申请号：US11670626

申请日：2007-02-02

申请人： Yung Feng Lin

发明人： Yung Feng Lin

IPC分类号： G11C16/06 ,  G11C7/02

CPC分类号： G11C7/062 ,  G11C16/28 ,  G11C2207/063 ,  H03F3/45273 ,  H03F2200/462 ,  H03F2200/91 ,  H03F2203/45096 ,  H03F2203/45098

摘要： A memory sensing circuit and method that can achieve both a wide read margin and a fast read time. Roughly described, a target cell draws a target cell current from a first node when selected. The target cell current depends on the charge level stored in the target cell. A reference cell draws a reference cell current from a second node when selected, and a current difference generator generates into a third node a third current flow positively dependent upon the difference between the target cell current and the reference cell current. The current difference generator also generates into a fourth node a fourth current flow negatively dependent upon the difference between the target cell current and the reference cell current. A sense amplifier has its first input connected to the third node and a second input connected to the fourth node.

摘要翻译： 一种可以实现宽读取余量和快速读取时间的存储器感测电路和方法。 粗略描述，当选择时，目标单元从第一节点绘制目标单元电流。 目标单元电流取决于存储在目标单元中的电荷水平。 当选择时，参考单元从第二节点绘制参考单元电流，并且电流差分发生器产生正向依赖于目标单元电流和参考单元电流之间的差的第三电流。 电流差分发生器还将第四电流流向第四节点产生负值，这取决于目标单元电流和参考单元电流之间的差异。 读出放大器的第一输入连接到第三节点，第二输入连接到第四节点。

公开(公告)号：US20080186786A1

公开(公告)日：2008-08-07

申请号：US11670626

申请日：2007-02-02

申请人： Yung Feng Lin

发明人： Yung Feng Lin

IPC分类号： G11C7/06

CPC分类号： G11C7/062 ,  G11C16/28 ,  G11C2207/063 ,  H03F3/45273 ,  H03F2200/462 ,  H03F2200/91 ,  H03F2203/45096 ,  H03F2203/45098

摘要： A memory sensing circuit and method that can achieve both a wide read margin and a fast read time. Roughly described, a target cell draws a target cell current from a first node when selected. The target cell current depends on the charge level stored in the target cell. A reference cell draws a reference cell current from a second node when selected, and a current difference generator generates into a third node a third current flow positively dependent upon the difference between the target cell current and the reference cell current. The current difference generator also generates into a fourth node a fourth current flow negatively dependent upon the difference between the target cell current and the reference cell current. A sense amplifier has its first input connected to the third node and a second input connected to the fourth node.

摘要翻译： 一种可以实现宽读取余量和快速读取时间的存储器感测电路和方法。 粗略描述，当选择时，目标单元从第一节点绘制目标单元电流。 目标单元电流取决于存储在目标单元中的电荷水平。 当选择时，参考单元从第二节点绘制参考单元电流，并且电流差分发生器产生正向依赖于目标单元电流和参考单元电流之间的差的第三电流。 电流差分发生器还将第四电流流向第四节点产生负值，这取决于目标单元电流和参考单元电流之间的差异。 读出放大器的第一输入连接到第三节点，第二输入连接到第四节点。

公开(公告)号：US4335358A

公开(公告)日：1982-06-15

申请号：US113928

申请日：1980-01-21

申请人： Werner H. Hoeft

发明人： Werner H. Hoeft

IPC分类号： H03F1/02 ,  H03F3/20 ,  H03F3/30 ,  H03F3/45

CPC分类号： H03F1/0261 ,  H03F3/3066 ,  H03F3/45071 ,  H03F2203/45098

摘要： A Class "B" amplifier circuit in which Class "B" conversion takes place in a converter portion of the circuit in combination with a differential amplifier input circuit, rather than in the output stage. The converter modulates the DC bias current supplied to the differential amplifier input circuit as a function of the input signal, in order to achieve Class "B" operation. The output amplifier portion of the circuit includes a pair of complementary, series-connected transistors, each of which is connected in a common-emitter configuration. The disclosed circuit provides a high input impedance and excellent dynamic range.

摘要翻译： “B”级放大器电路，其中类别“B”转换在电路的转换器部分中与差分放大器输入电路组合而不是在输出级中进行。 转换器根据输入信号调制提供给差分放大器输入电路的直流偏置电流，以实现“B”类。 电路的输出放大器部分包括一对互补的串联连接的晶体管，每个晶体管以共发射极配置连接。 所公开的电路提供高输入阻抗和优异的动态范围。