公开(公告)号：US20240012616A1

公开(公告)日：2024-01-11

申请号：US17811846

申请日：2022-07-11

申请人： Micron Technology, Inc.

发明人： Keith A. Benjamin

IPC分类号： G06F7/544

CPC分类号： G06F7/5443 ,  G06F2207/581

摘要： Methods, systems, and devices for a programmable finite field generator for memory are described. In some cases, a system (e.g., a memory system, a host system) may store coefficient values indicating Galois Field multipliers in an array of configuration registers associated with a finite field generator. To update a set of values stored in a set of registers associated with the finite field generator, the system may perform a set of Galois Field multiplication operations according to Galois Field multipliers indicated by the coefficient values stored in the array of configuration registers. The system may perform at least one Galois Field summation operation on one or more of the multiplied values to generate an updated value. Then, the system may store the updated value in a first register from the set of registers, and shift the set of values along the remaining set of registers.

公开(公告)号：US20160036464A1

公开(公告)日：2016-02-04

申请号：US14445782

申请日：2014-07-29

申请人： Storart Technology Co., Ltd.

发明人： Jui Hui HUNG ,  Chih Nan YEN

IPC分类号： H03M13/15

CPC分类号： H03M13/1545 ,  G06F2207/581 ,  G11B20/1833 ,  H03M13/151 ,  H03M13/152 ,  H03M13/158 ,  H03M13/27 ,  H03M13/29 ,  H03M13/6516

摘要： The present invention discloses a multi-code Chien's search circuit for BCH codes with various values of m in GF(2m). The circuit includes: a combined matrix unit, a number of first multiplexers, a number of registers and a number of second multiplexers. By designing the Chien's search circuit having several Chien's search matrices, with peripheral components, it is able to achieve applications for different code rates, different code lengths and even different m in GF(2m).

摘要翻译： 本发明公开了一种用于在GF（2m）中具有各种m值的BCH码的多码Chien搜索电路。 该电路包括：组合矩阵单元，多个第一多路复用器，多个寄存器和多个第二多路复用器。 通过设计Chien的搜索电路，具有几个Chien的搜索矩阵，具有外围组件，可以在GF（2m）中实现不同码率，不同码长，甚至不同m的应用。

公开(公告)号：US08880574B2

公开(公告)日：2014-11-04

申请号：US13120914

申请日：2008-09-24

申请人： Jochen Rivoir

发明人： Jochen Rivoir

IPC分类号： G06F7/38 ,  H03K3/84 ,  G06F7/58

CPC分类号： H03K3/84 ,  G06F7/584 ,  G06F2207/581 ,  G06F2207/582

摘要： An embodiment of a state machine for generating a pseudo-random word stream, each word of the word stream including a plurality of subsequent bits of a pseudo-random bit sequence includes a plurality of clock registers and a feedback circuit coupled to the registers and adapted to provide a plurality of feedback signals to the registers based on a feedback function and a plurality of register output signals of the registers, wherein the state machine is configured such that a first word defined by the plurality of register output signals includes a first set of subsequent bits of a pseudo-random bit stream and such that a subsequent second word defined by the plurality of register output signals includes a second set of subsequent bits of a pseudo-random bit stream.

摘要翻译： 一种用于产生伪随机字流的状态机的实施例，包括伪随机位序列的多个后续位的字流的每个字包括多个时钟寄存器和耦合到寄存器并被适配的反馈电路 基于所述寄存器的反馈功能和多个寄存器输出信号向所述寄存器提供多个反馈信号，其中所述状态机被配置为使得由所述多个寄存器输出信号定义的第一字包括第一组 伪随机比特流的后续比特，并且使得由多个寄存器输出信号定义的后续第二字包括伪随机比特流的第二组后续比特。

公开(公告)号：US06883717B1

公开(公告)日：2005-04-26

申请号：US10709112

申请日：2004-04-14

申请人： Edward E. Kelley ,  Franco Motika

发明人： Edward E. Kelley ,  Franco Motika

IPC分类号： G06F7/58 ,  G07F7/10 ,  G07F7/12 ,  G07F19/00 ,  G06K5/00 ,  G06K19/06

CPC分类号： G07F7/1008 ,  G06F2207/581 ,  G06Q20/341 ,  G06Q20/40145 ,  G06Q20/40975 ,  G07F7/08 ,  G07F7/1016 ,  G07F7/12

摘要： A secure credit card has a pair of linear feedback shift registers (LFSRs) for generating a pair of random numbers. The LFSRs each have a unique initial state and feedback tap configuration. Hence, they each produce a unique sequence of numbers. When a financial transaction occurs, the LFSRs are operated for a random number of clock cycles, to create a pair of matched random numbers. Each card issued has unique LFSR settings, and so will produce characteristic random numbers. At a financial institution, the LFSR settings are known, so the financial institution can determine by calculation if the pair of random numbers is authentic. There are many variations, including a credit card with a secret security code for activation, and 2-way “handshake” communication with the financial institution. Also, one of the LFSRs may be replaced with a binary, or similar counter.

摘要翻译： 一个安全的信用卡有一对用于产生一对随机数的线性反馈移位寄存器（LFSR）。 LFSR每个都具有唯一的初始状态和反馈抽头配置。 因此，它们各自产生唯一的数字序列。 当金融交易发生时，LFSR以随机数的时钟周期运行，以创建一对匹配的随机数。 发行的每个卡都具有独特的LFSR设置，因此会产生特征随机数。 在金融机构，LFSR设置是已知的，所以金融机构可以通过计算确定一对随机数是否可信。 有许多变化，包括具有激活的秘密安全码的信用卡和与金融机构的双向“握手”通信。 此外，其中一个LFSR可以被替换为二进制或类似的计数器。

公开(公告)号：US06754345B2

公开(公告)日：2004-06-22

申请号：US09837484

申请日：2001-04-19

申请人： Junichi Ishimoto ,  Masanori Tanaka

发明人： Junichi Ishimoto ,  Masanori Tanaka

IPC分类号： H04L900

CPC分类号： G06F7/584 ,  G06F2207/581 ,  G06F2207/583

摘要： A pseudorandom number generation circuit 2 whose generation timings of pseudorandom numbers vary randomly is disclosed. The pseudorandom number generation circuit 2 includes a clock generation circuit 4 which generates four kinds of clocks, a selection signal generation circuit 8 which generates selection signals randomly, a selection circuit 6 which selects either one of the four kinds of clocks based on the selection signals, and a linear feedback shift register (LFSR) 10 which carries out shift operation based on the clock selected by the selection circuit 6. The LFSR 10 generates a pseudorandom number in response to the selected clocks. Since the selection of the clock is carried out randomly by the selection signal generation circuit 8, the generation timings of the pseudorandom numbers generated by the LFSR 10 are also random.

摘要翻译： 公开了伪随机数的随机定时的随机变化的伪随机数生成电路2。 伪随机数生成电路2包括产生四种时钟的时钟生成电路4，随机生成选择信号的选择信号生成电路8，选择电路6，其根据选择信号选择四种时钟之一 以及基于由选择电路6选择的时钟执行移位操作的线性反馈移位寄存器（LFSR）10 .LFSR 10响应于所选择的时钟产生伪随机数。 由于选择信号生成电路8随机地进行时钟的选择，所以由LFSR 10生成的伪随机数的生成定时也是随机的。

公开(公告)号：US20010033663A1

公开(公告)日：2001-10-25

申请号：US09837484

申请日：2001-04-19

发明人： Junichi Ishimoto ,  Masanori Tanaka

IPC分类号： H04L009/26 ,  G06F007/58

CPC分类号： G06F7/584 ,  G06F2207/581 ,  G06F2207/583

摘要： A pseudorandom number generation circuit 2 whose generation timings of pseudorandom numbers vary randomly is disclosed. The pseudorandom number generation circuit 2 includes a clock generation circuit 4 which generates four kinds of clocks, a selection signal generation circuit 8 which generates selection signals randomly, a selection circuit 6 which selects either one of the four kinds of clocks based on the selection signals, and a linear feedback shift register (LFSR) 10 which carries out shift operation based on the clock selected by the selection circuit 6. The LFSR 10 generates a pseudorandom number in response to the selected clocks. Since the selection of the clock is carried out randomly by the selection signal generation circuit 8, the generation timings of the pseudorandom numbers generated by the LFSR 10 are also random.

公开(公告)号：US06292506B1

公开(公告)日：2001-09-18

申请号：US09205313

申请日：1998-12-04

申请人： John F. Brendle, Jr. ,  James P. Stephens, Sr. ,  Michael A. Temple ,  Robert S. Parks

发明人： John F. Brendle, Jr. ,  James P. Stephens, Sr. ,  Michael A. Temple ,  Robert S. Parks

IPC分类号： H04L1528

CPC分类号： G06F7/584 ,  G06F2207/581 ,  G06F2207/583

摘要： A method and device for generating a pseudorandom electrical signal for enabling spread spectrum communication scrambling by directing data entry into pseudorandom number generator integrated circuit chip controlling registers using a length selectable feedback logic data sequence and either computer programmable selector means or manual selector means to communicate the logic data sequence characters to buffers. The logic data sequence characters are clocked to a pseudorandom number generating register of an integrated circuit chip and the pseudorandom electrical signal is generated by selectively tapping a signal code therefrom. The method and device features a pseudorandom electrical signal length varying capability and is portable to various laboratory applications without a change in hardware configuration.

摘要翻译： 一种用于通过使用长度可选择反馈逻辑数据序列和计算机可编程选择器装置或手动选择器装置将数据输入引导到伪随机数发生器集成电路芯片控制寄存器来产生用于实现扩频通信加扰的伪随机电信号的方法和装置， 逻辑数据序列字符到缓冲区。 逻辑数据序列字符被计时到集成电路芯片的伪随机数产生寄存器，并且通过有选择地从其中窃取信号代码产生伪随机电信号。 该方法和装置具有伪随机电信号长度变化能力，并可在不改变硬件配置的情况下便携到各种实验室应用。

公开(公告)号：US6067359A

公开(公告)日：2000-05-23

申请号：US82029

申请日：1998-05-21

申请人： Michio Shimada

发明人： Michio Shimada

IPC分类号： G06F7/58 ,  G09C1/00 ,  H03K3/84 ,  H04L9/26 ,  H04K1/00

CPC分类号： G06F7/584 ,  G06F2207/581

摘要： A pseudorandom number sequence generator comprises a bidirectional shift register arranged to be loaded with a multi-bit sequence. The shift register is responsive to an ith clock pulse and an ith direction control bit for shifting the multi-bit sequence in one of two directions, delivering an ith output bit and receiving an ith input bit. The multi-bit sequence successively defines one of nodes of an Eulerian graph connected by branches. A feedback circuit is connected to the shift register for converting a set of input data to a set of output data. The input data comprises a multi-bit sequence stored in the shift register in response to an (i+1)th clock pulse, the ith output bit and the ith direction control bit and the output data comprises an (i+1)th input bit and an (i+1)th direction control bit. The output data is supplied to the shift register so that multi-bit sequences produced by the shift register move around the graph following every branch exactly once, and outputting the (i+1)th input bit to form a pseudorandom number sequence.

摘要翻译： 伪随机数序列发生器包括布置为加载多比特序列的双向移位寄存器。 移位寄存器响应第i个时钟脉冲和第i个方向控制位，用于在两个方向中的一个方向上移位多位序列，传送第i个输出位和接收第i个输入位。 多比特序列连续地定义了由分支连接的欧拉图的一个节点。 反馈电路连接到移位寄存器，用于将一组输入数据转换成一组输出数据。 输入数据包括响应于第（i + 1）个时钟脉冲存储在移位寄存器中的第i个输出位和第i个方向控制位的多位序列，并且输出数据包括第（i + 1）个输入 位和第（i + 1）个方向控制位。 将输出数据提供给移位寄存器，使得由移位寄存器产生的多位序列在每个分支正好一次之后绕图形移动，并且输出第（i + 1）个输入位以形成伪随机数序列。

公开(公告)号：US5596617A

公开(公告)日：1997-01-21

申请号：US495493

申请日：1995-09-12

申请人： Andreas Wolf ,  Hans W. Ahrweiler

发明人： Andreas Wolf ,  Hans W. Ahrweiler

IPC分类号： G06F7/58 ,  H03K3/84

CPC分类号： G06F7/584 ,  H03K3/84 ,  G06F2207/581 ,  G06F2207/583

摘要： A feedback shift register for generating digital signals representing pseudo-random number sequences has n-stages and exclusive OR-circuits in the feedback logic, as well as a clock-pulse generator. To be able to generate digital signals, which are well suited for a further digital processing, the clock-pulse generator (17) is linked with the n-stages (11, 12, 13, 14, 15) of the shift register (10) via a controllable gate circuit (18), which blocks one clock pulse of 2.sup.n clock pulses (CLK) of the clock-pulse generator (17) in each case.

摘要翻译： PCT No.PCT / DE94 / 00091 Sec。 371 1995年9月12日第 102（e）日期1995年9月12日PCT 1994年1月26日PCT公布。 第WO94 / 17591号公报 日期1994年8月4日用于产生表示伪随机数序列的数字信号的反馈移位寄存器在反馈逻辑中具有n级和异或电路，以及时钟脉冲发生器。 为了能够产生非常适合进一步数字处理的数字信号，时钟脉冲发生器（17）与移位寄存器（10）的n级（11,12,13,14,15）链接 ）通过可控制的栅极电路（18），其在每种情况下阻塞时钟脉冲发生器（17）的2n个时钟脉冲（CLK）的一个时钟脉冲。

公开(公告)号：US5463638A

公开(公告)日：1995-10-31

申请号：US46832

申请日：1993-04-13

申请人： Willem J. De Lange

发明人： Willem J. De Lange

IPC分类号： G06F3/00 ,  G01R31/28 ,  G01R31/3183 ,  G01R31/3185 ,  G01R31/319 ,  G06F7/58 ,  G06F11/22 ,  G06F11/277 ,  H04B17/00

CPC分类号： G01R31/31908 ,  G01R31/318547 ,  G01R31/31905 ,  G01R31/31921 ,  G06F7/584 ,  G06F11/277 ,  G06F2207/581 ,  G06F2207/583

摘要： There is disclosed a control device for interfacing between a test machine and electronic circuitry under test. The test machine generates a pattern that is composited with background data in a predetermined configuration. Each output bit is specified as either foreground or background through an indicator memory. Foreground data and background data are put at their intended positions while using a barrel shifter, decompressing means and an output multiplexer. After the test, a counterpart procedure is used for extracting exclusively relevant data at the expense of dummy data.

摘要翻译： 公开了一种用于在测试机和被测电子电路之间进行接口的控制装置。 测试机器生成与预定配置中的背景数据合成的模式。 每个输出位通过指示存储器指定为前景或背景。 在使用桶形移位器，解压缩装置和输出多路复用器的同时，将前景数据和背景数据放在其预定位置。 在测试之后，使用相应的过程以牺牲虚拟数据为代价来提取相关数据。