公开(公告)号：US09018978B2

公开(公告)日：2015-04-28

申请号：US14261886

申请日：2014-04-25

申请人： Tabula, Inc.

发明人： Brad Hutchings ,  Jason Redgrave ,  Teju Khubchandani ,  Herman Schmit ,  Steven Teig

IPC分类号： G06F7/38 ,  H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1731 ,  H03K19/177 ,  H03K19/17704 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/17756 ,  H03K19/17764

摘要： A novel configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations is provided. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. The configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. The configuration network is a pipelined network.

摘要翻译： 提供了一种新颖的可配置集成电路（IC），其具有用于可配置地执行不同操作的多个可配置电路。 在IC的操作期间，每个特定可配置电路执行由针对特定可配置电路的特定配置数据集指定的特定操作。 当IC操作并且第一组可配置电路执行第一组操作时，从IC的外部加载配置数据，用于配置第二组可配置电路。 可配置IC包括用于从IC外部从IC快速加载配置数据的配置网络。 配置网络是流水线网络。

公开(公告)号：US09018977B2

公开(公告)日：2015-04-28

申请号：US14181557

申请日：2014-02-14

申请人： Tabula Inc.

发明人： Jason Redgrave ,  Herman Schmit

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/17744

摘要： Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions. The configurable IC also includes a set of configurable routing circuits for routing signals to and from the configurable circuits. During several operational cycles of the configurable IC, a set of data registers are defined by the configurable routing circuits. These data registers may be used wherever a flip-flop can be used.

摘要翻译： 本发明的一些实施例提供了可配置的集成电路（“IC”）。 可配置IC包括用于可配置地执行一组功能的一组可配置逻辑电路。 可配置IC还包括一组可配置路由电路，用于将信号路由到可配置电路和从可配置电路路由信号。 在可配置IC的几个操作周期期间，一组数据寄存器由可配置的路由电路定义。 这些数据寄存器可以用于可以使用触发器的地方。

公开(公告)号：US09000801B1

公开(公告)日：2015-04-07

申请号：US13802655

申请日：2013-03-13

申请人： Tabula, Inc.

发明人： Christopher D. Ebeling ,  Michael Glenn Wrighton ,  Andrew Caldwell ,  Kent Townley

IPC分类号： H03K19/177 ,  H03K19/173

CPC分类号： H03K19/173

摘要： An integrated circuit (IC) that includes multiple clock domains is provided. Each clock domain operates at a user specified data rate, and the data rates of at least two of the clock domains are related by a common base clock. The specified data rate of each clock domain is controlled by a modulating signal. Each clock domain includes reconfigurable circuits that operate on the common base clock, and the modulating signal controls the data rate of the clock domain by modulating reconfiguration of the reconfigurable circuits. The reconfigurable circuits reconfigure when the modulating signal enables the reconfiguration.

摘要翻译： 提供了包括多个时钟域的集成电路（IC）。 每个时钟域以用户指定的数据速率运行，并且至少两个时钟域的数据速率通过公共基准时钟相关。 每个时钟域的指定数据速率由调制信号控制。 每个时钟域包括在公共基准时钟上工作的可重新配置的电路，并且调制信号通过调制可重构电路的重新配置来控制时钟域的数据速率。 当调制信号使能重新配置时，可重配置电路重新配置。

公开(公告)号：US20150077158A1

公开(公告)日：2015-03-19

申请号：US14246955

申请日：2014-04-07

申请人： Tabula, Inc.

发明人： Steven Teig ,  Herman Schmit ,  Randy Renfu Huang

IPC分类号： H03K19/177

CPC分类号： H03K19/17704 ,  H03K19/17736

摘要： Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.

摘要翻译： 一些实施例提供了一种可配置IC，其包括具有存储元件的可配置路由结构。 在一些实施例中，路由结构提供将信号路由到来自源和目的地组件的信号通路。 一些实施例的路由结构提供了选择性地将通过路由结构的信号存储在路由结构的存储元件内的能力。 以这种方式，源或目的地组件连续地执行操作（例如，计算或路由），而不管来自或向这样的组件的先前信号是否存储在路由结构内。 源和目标组件包括可配置逻辑电路，可配置互连电路以及在整个可配置IC中接收或分配信号的各种其他电路。

公开(公告)号：US20150054546A1

公开(公告)日：2015-02-26

申请号：US14222548

申请日：2014-03-21

申请人： Tabula, Inc.

发明人： Jason Redgrave

IPC分类号： H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/17736

摘要： Some embodiments provide a circuit for accessing stored data in a configurable IC that includes several configurable circuits. The IC also includes several storage circuits. Each storage circuit has (1) several storage elements for storing data for the configurable circuits, and (2) output circuitry for outputting data stored in the storage elements. The output circuitry includes a first set of interconnects for receiving at least a first repeating periodic signal and for periodically outputting data from at least two storage elements to the configurable circuits.

摘要翻译： 一些实施例提供用于访问包括若干可配置电路的可配置IC中的存储数据的电路。 IC还包括几个存储电路。 每个存储电路具有（1）用于存储可配置电路的数据的几个存储元件，和（2）用于输出存储在存储元件中的数据的输出电路。 输出电路包括用于接收至少第一重复周期性信号的第一组互连，并且用于周期性地将数据从至少两个存储元件输出到可配置电路。

公开(公告)号：US08941409B2

公开(公告)日：2015-01-27

申请号：US13540596

申请日：2012-07-02

申请人： Martin Voogel ,  Steven Teig ,  Trevis Chandler

发明人： Martin Voogel ,  Steven Teig ,  Trevis Chandler

IPC分类号： H03K19/177

CPC分类号： H03K19/177 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H03K19/018585 ,  H03K19/17704 ,  H03K19/17744 ,  H03K19/17748 ,  H03K19/1776 ,  H01L2924/00014 ,  H01L2924/00

摘要： An integrated circuit (“IC”) having configurable logic circuits for configurably performing multiple different logic operations based on configuration data is provided. The IC includes a configurable routing fabric for configurably routing signals among configurable logic circuits. The configurable routing fabric includes a particular wiring path that connects an output of a source circuit to inputs of a destination circuit. The particular wiring path includes a first path and a second path that is parallel to the first path. The first and second paths are for configurably storing output signals of the source circuit. The first path connects to a first input of the destination circuit and the second path connects to a second input of the destination path.

摘要翻译： 提供具有可配置逻辑电路的集成电路（“IC”），用于基于配置数据可配置地执行多个不同的逻辑操作。 该IC包括可配置的布线结构，用于在可配置逻辑电路之间可配置地路由信号。 可配置路由布线包括将源电路的输出连接到目的地电路的输入的特定布线路径。 特定布线路径包括平行于第一路径的第一路径和第二路径。 第一和第二路径用于可配置地存储源电路的输出信号。 第一路径连接到目的地电路的第一输入端，第二路径连接到目的地路径的第二输入端。

公开(公告)号：US20140317588A1

公开(公告)日：2014-10-23

申请号：US14261919

申请日：2014-04-25

申请人： Tabula, Inc.

发明人： Steven Teig ,  Andrew Caldwell

IPC分类号： G06F17/50 ,  H03K19/173

CPC分类号： G06F17/5081 ,  G06F17/5054 ,  G06F2217/84 ,  H03K19/1731 ,  H03K19/17748

摘要： Some embodiments provide a method that identifies a first physical design solution for positioning several configurable operations on several reconfigurable circuits of an integrated circuit (IC). The method identifies a second physical design solution for positioning the configurable operations on the configurable circuits. One of the identified physical design solutions has one reconfigurable circuit perform a particular configurable operation in at least two reconfiguration cycles while the other identified solution does not have one reconfigurable circuit perform the particular configurable operation in two reconfiguration cycles. The method costs the first and second physical design solutions. The method selects one of the two physical design solutions based on the costs.

摘要翻译： 一些实施例提供了一种识别用于在集成电路（IC）的几个可重新配置的电路上定位多个可配置操作的第一物理设计解决方案的方法。 该方法识别用于将可配置操作定位在可配置电路上的第二物理设计解决方案。 所识别的物理设计解决方案之一具有一个可重构电路在至少两个重新配置周期中执行特定的可配置操作，而另一个识别的解决方案没有一个可重配置电路在两个重新配置周期中执行特定的可配置操作。 该方法花费第一和第二物理设计解决方案。 该方法基于成本选择两种物理设计方案之一。

公开(公告)号：US20140210512A1

公开(公告)日：2014-07-31

申请号：US14166667

申请日：2014-01-28

申请人： Tabula, Inc.

发明人： Scott J. Weber ,  Christopher D. Ebeling ,  Andrew Caldwell ,  Steven Teig ,  Timothy J. Callahan ,  Hung Q. Nguyen ,  Shangzhi Sun ,  Shilpa V. Yeole

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  G06F17/505

摘要： A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.

摘要翻译： 公开了一种通过在IC的设计中重新缩放原始电路组来设计集成电路（“IC”）的新颖方法。 要重新定标的原始电路组包括顺序节点，组合节点和互连。 每个顺序节点与时钟的相位相关联。 该方法产生包括电路的多个复制集合的重新定标的电路集合。 每个电路副本集包括与原始电路组中的节点和互连相同的顺序节点，组合节点和互连。 每个顺序节点与时钟的相位相关联，时钟的相位是原始集合中其对应的顺序元素的相位的一小部分。 该方法将每个电路副本中的节点连接到另一个副本集中的逻辑等效节点。 该方法用重新定标的电路组替换原始电路组。

公开(公告)号：US08788987B2

公开(公告)日：2014-07-22

申请号：US13806767

申请日：2011-04-06

申请人： Scott J. Weber ,  Christopher D. Ebeling ,  Andrew Caldwell ,  Steven Teig ,  Timothy J. Callahan ,  Hung Q. Nguyen ,  Shangzhi Sun ,  Shilpa V. Yeole

发明人： Scott J. Weber ,  Christopher D. Ebeling ,  Andrew Caldwell ,  Steven Teig ,  Timothy J. Callahan ,  Hung Q. Nguyen ,  Shangzhi Sun ,  Shilpa V. Yeole

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5054

摘要： A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.

公开(公告)号：US08598907B2

公开(公告)日：2013-12-03

申请号：US13360646

申请日：2012-01-27

申请人： Trevis Chandler ,  Joe Entjer ,  Martin Voogel ,  Jason Redgrave

发明人： Trevis Chandler ,  Joe Entjer ,  Martin Voogel ,  Jason Redgrave

IPC分类号： H03K19/173

CPC分类号： H03K19/0008 ,  G06F15/7867 ,  G11C7/1045 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H03K3/0372 ,  H03K19/17732 ,  H03K19/17748 ,  H03K19/17752 ,  H03K19/17768 ,  H01L2924/00 ,  H01L2924/00014

摘要： Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.

摘要翻译： 一些实施例向IC提供配置上下文切换器。 IC包括几个可配置电路，每个可配置电路可以在任何给定时间根据当时接收到的配置数据集配置执行多个操作之一。 IC包括多个存储电路，用于存储每个可配置电路的几个配置数据组。 IC还包括用于将可配置电路可切换地连接到不同组的存储电路以接收不同组的配置数据集的上下文切换互连电路。 上下文切换器包括用于重新定时来自配置存储元件的数据的一个或多个阶段。 这些阶段可以包括互连电路或存储电路。 一些实施例构建配置数据存储元件中的一个阶段。 一些实施例对配置数据位进行编码，并因此利用上下文切换器中的解码器对编码的配置数据进行解码。