公开(公告)号：US09047431B2

公开(公告)日：2015-06-02

申请号：US14311361

申请日：2014-06-23

申请人： Tabula, Inc.

发明人： Eric A. Sather ,  Steven Teig

IPC分类号： G06F17/50 ,  G06F15/177 ,  G06F9/00

CPC分类号： G06F17/5054 ,  G06F9/00 ,  G06F15/177 ,  G06F17/16 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

摘要： A system and method of determining paths of components when placing and routing configurable circuits. The method identifies a probabilistic data flow through multiple components using a simplified connection matrix. The simplified connection matrix is used to determine a probabilistic data flow through the components without data flowing from any component to itself. The probabilistic data flow is used to determine a probabilistic data flow through the components with some of the components having data flowing from themselves back to themselves. The probabilistic data flow through each component and the number of inputs of the components are used to determine a cost for each component. The cost of a path through the circuit is determined from the costs of the individual components in the path. The costs of the components are used to determine which path of components to use.

摘要翻译： 在配置和布线可配置电路时确定组件路径的系统和方法。 该方法使用简化的连接矩阵来识别通过多个组件的概率数据流。 简化的连接矩阵用于确定通过组件的概率数据流，而没有数据从任何组件流向自身。 概率数据流用于确定通过组件的概率数据流，其中一些组件具有从自身返回到自身的数据。 通过每个组件的概率数据流和组件的输入数量用于确定每个组件的成本。 通过电路的路径的成本由路径中各个组件的成本确定。 组件的成本用于确定要使用的组件路径。

公开(公告)号：US09041430B2

公开(公告)日：2015-05-26

申请号：US14166680

申请日：2014-01-28

申请人： Tabula, Inc.

发明人： Andre Rohe ,  Steven Teig ,  Herman Schmit ,  Jason Redgrave ,  Andrew Caldwell

IPC分类号： H03K19/173 ,  H03K19/177 ,  G06F17/50

CPC分类号： G06F17/5054 ,  G06F17/5077 ,  H03K19/173 ,  H03K19/17736 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/17776

摘要： An integrated circuit (IC) with a novel configurable routing fabric is provided. The configurable routing fabric has signal paths that propagate signals between user registers on user clock cycles. Each signal path includes a set of configurable storage elements and a set of configurable logic elements. Each configurable storage element in the path is reconfigurable on every sub-cycle of the user clock cycle to either store an incoming signal or to pass the incoming signal transparently.

摘要翻译： 提供了一种具有新型可配置布线结构的集成电路（IC）。 可配置的路由结构具有在用户时钟周期内在用户寄存器之间传播信号的信号路径。 每个信号路径包括一组可配置的存储元件和一组可配置的逻辑元件。 路径中的每个可配置存储元件可在用户时钟周期的每个子周期上重新配置，以存储输入信号或透明地传递输入信号。

公开(公告)号：US20150012782A1

公开(公告)日：2015-01-08

申请号：US14281219

申请日：2014-05-19

申请人： Tabula, Inc.

发明人： Andrea Olgiati ,  Matthew Pond Baker ,  Steven Teig

IPC分类号： G06F11/34

CPC分类号： G06F11/263 ,  G01R31/2851 ,  G01R31/3177 ,  G01R31/3185 ,  G06F11/079 ,  G06F11/2205 ,  G06F11/3003 ,  G06F11/3409 ,  G06F11/3466 ,  G06F17/5027 ,  G06F17/5054 ,  G06F17/5081 ,  G06F2201/86 ,  H03K19/17756

摘要： An application-specific integrated circuit (ASIC) is provided. The ASIC includes a group of non-configurable circuits customized for performing operations for a particular use. The ASIC also includes a set of reconfigurable circuits for configurably performing a set of operations based on configuration data. The ASIC also includes a configuration and monitoring network that receives a set of signals from the non-configurable circuits of the ASIC. The configuration and monitoring network also receives incremental sets of configuration data while the ASIC is performing operations of the user design. Each incremental set of data is used for reconfiguring the configuration and monitoring network (i) to monitor one or more signals in the set of signals and (ii) to take a set of actions when values of the monitored signals satisfy a condition.

摘要翻译： 提供专用集成电路（ASIC）。 ASIC包括为特定用途执行操作而定制的一组不可配置电路。 ASIC还包括一组用于可配置地基于配置数据执行一组操作的可重新配置电路。 ASIC还包括从ASIC的不可配置电路接收一组信号的配置和监控网络。 当ASIC正在执行用户设计的操作时，配置和监视网络还接收增量的配置数据集。 每个增量数据集用于重新配置和监视网络（i）以监视该组信号中的一个或多个信号，以及（ii）当所监视的信号的值满足条件时采取一组动作。

公开(公告)号：US20150008957A1

公开(公告)日：2015-01-08

申请号：US14281262

申请日：2014-05-19

申请人： Tabula, Inc.

发明人： Andrea Olgiati ,  Matthew Pond Baker ,  Steven Teig

IPC分类号： H03K19/177 ,  G01R31/26

CPC分类号： G06F11/263 ,  G01R31/2851 ,  G01R31/3177 ,  G01R31/3185 ,  G06F11/079 ,  G06F11/2205 ,  G06F11/3003 ,  G06F11/3409 ,  G06F11/3466 ,  G06F17/5027 ,  G06F17/5054 ,  G06F17/5081 ,  G06F2201/86 ,  H03K19/17756

摘要： A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an incremental second set of configuration data based on the definition of the event and the set of corresponding actions. While the first IC is performing the operations of the user design, the method loads the incremental second set of configuration data into the first IC and monitors the signals received from the second IC at the first IC.

摘要翻译： 监视一组IC的操作的方法。 该方法将第一组配置数据加载到第一IC中，用于配置第一IC的一组可配置电路以执行用户设计的操作。 该方法基于用户设计中的一组信号的值和在事件发生时采取的一组对应的动作来接收事件的定义。 该组信号包括从第二IC接收的至少一个信号。 该方法基于事件的定义和相应动作的集合生成增量的第二组配置数据。 当第一IC正在执行用户设计的操作时，该方法将增量的第二组配置数据加载到第一IC中并监视在第一IC处从第二IC接收到的信号。

公开(公告)号：US20150002190A1

公开(公告)日：2015-01-01

申请号：US14324515

申请日：2014-07-07

申请人： Tabula, Inc.

发明人： Randy R. Huang ,  Martin Voogel ,  Jingcao Hu ,  Steven Teig

IPC分类号： H03K19/00 ,  H03K19/177

CPC分类号： H03K19/0008 ,  G06F17/50 ,  G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  H03K19/1737 ,  H03K19/17748 ,  H03K19/17756 ,  H03K19/17784 ,  H03K19/17796

摘要： A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration.

摘要翻译： 一种用于降低可重构集成电路中的功耗的系统和方法。 一些实施例提供了减少要重新配置的比特数的布局和路由程序。 一些实施例提供了放置和路由程序，其增加了在某些时间不需要重新配置的电路组的数量。 一些实施例包括选择性地阻止重新配置的电路。

公开(公告)号：US20140007027A1

公开(公告)日：2014-01-02

申请号：US14016057

申请日：2013-08-31

申请人： Tabula, Inc.

发明人： Andrew Caldwell ,  Steven Teig

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/505 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081

摘要： An abstract decision module primitive for placement within a logical representation (i.e., a netlist) of a circuit design is described. The decision module primitive receives as inputs alternative solutions for a given function or segment of a netlist. The alternative solutions include functionally equivalent, but structurally different implementations of the function or segment of the netlist. The decision module primitive alternatively selects between connecting one of the inputs to the netlist to provide a complete functional definition for the netlist based on constraint information.The selected input of the decision module may be updated as additional constraint information is determined throughout the various stages of the design process. In addition, alternative solutions for a given function or segment of the netlist may be added to and/or removed from the inputs of a decision module as additional constraint information is identified.

摘要翻译： 描述了用于放置在电路设计的逻辑表示（即，网表中）的抽象决策模块原语。 决策模块原语接收网表的给定功能或段的输入替代解决方案。 替代解决方案包括功能等同，但在网表的功能或段的结构上不同的实现。 所述决策模块基元可选择在连接到所述网表之一的输入之间，以基于约束信息为所述网表提供完整的功能定义。 当在设计过程的各个阶段确定附加约束信息时，可以更新决策模块的所选择的输入。 此外，当识别出额外的约束信息时，可以向决策模块的输入添加和/或从其中删除网表的给定功能或段的替代解决方案。

公开(公告)号：US20130147514A1

公开(公告)日：2013-06-13

申请号：US13679981

申请日：2012-11-16

申请人： Tabula, Inc.

发明人： Trevis Chandler ,  Jason Redgrave ,  Martin Voogel

IPC分类号： H03K19/177

CPC分类号： H03K19/0008 ,  G06F15/7867 ,  G11C7/1045 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H03K3/0372 ,  H03K19/17732 ,  H03K19/17748 ,  H03K19/17752 ,  H03K19/17768 ,  H01L2924/00 ,  H01L2924/00014

摘要： Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.

摘要翻译： 一些实施例向IC提供配置上下文切换器。 IC包括几个可配置电路，每个可配置电路可以在任何给定时间根据当时接收到的配置数据集配置执行多个操作之一。 IC包括多个存储电路，用于存储每个可配置电路的几个配置数据组。 IC还包括用于将可配置电路可切换地连接到不同组的存储电路以接收不同组的配置数据集的上下文切换互连电路。 上下文切换器包括用于重新定时来自配置存储元件的数据的一个或多个阶段。 这些阶段可以包括互连电路或存储电路。 一些实施例构建配置数据存储元件中的一个阶段。 一些实施例对配置数据位进行编码，并因此利用上下文切换器中的解码器对编码的配置数据进行解码。

公开(公告)号：US20150234008A1

公开(公告)日：2015-08-20

申请号：US14627856

申请日：2015-02-20

申请人： Tabula, Inc.

发明人： Marc Miller ,  Steven Teig ,  Jason Redgrave ,  Brad Hutchings ,  Danny Thom

IPC分类号： G01R31/3177

CPC分类号： G01R31/3177 ,  G06F11/221 ,  G11C2029/0409

摘要： Some embodiments provide an integrated circuit (“IC”) with a primary circuit structure. The primary circuit structure is for performing multiple operations that implement a user design. The primary circuit structure includes multiple circuits. The IC also includes a secondary monitoring structure for monitoring multiple operations. The secondary monitoring structure includes a network communicatively coupled to multiple circuits of the primary circuit structure. The secondary monitoring circuit structure is for analyzing the monitored operations and reporting on the analysis to a circuit outside of the IC.

摘要翻译： 一些实施例提供具有主电路结构的集成电路（“IC”）。 主电路结构用于执行实现用户设计的多个操作。 主电路结构包括多个电路。 IC还包括用于监视多个操作的二级监视结构。 辅助监视结构包括通信地耦合到主电路结构的多个电路的网络。 二次监视电路结构用于分析被监控的操作并将分析报告给IC外的电路。

公开(公告)号：US20150137851A1

公开(公告)日：2015-05-21

申请号：US14311359

申请日：2014-06-23

申请人： Tabula, Inc.

发明人： Herman Schmit ,  Jason Redgrave

IPC分类号： G06F7/506 ,  H03K19/173

CPC分类号： G06F7/506 ,  G06F2207/3868 ,  H03K19/173

摘要： Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.

摘要翻译： 一些实施例提供了包括若干可配置逻辑电路的可配置IC，其中逻辑电路包括若干组相关联的可配置逻辑电路。 对于每组几组相关联的可配置逻辑电路，可重新配置的IC还包括一个执行多达N个进位操作的进位电路，其中N大于2。

公开(公告)号：US20150130508A1

公开(公告)日：2015-05-14

申请号：US14331191

申请日：2014-07-14

申请人： TABULA, INC.

发明人： Herman Schmit ,  Michael Butts ,  Brad L. Hutchings ,  Steven Teig

IPC分类号： H03K19/177

CPC分类号： G06F17/5068 ,  H03K19/17748 ,  H03K19/17752 ,  H03K19/17776

摘要： Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a set of operations. At least a first configurable circuit reconfigures at a first reconfiguration rate. The first configurable circuit performs a different operation each time the first configurable circuit is reconfigured. The reconfiguration of the first configurable circuit does not follow any sequential progression through the set of operations of the first configurable circuit.