公开(公告)号：US20130093460A1

公开(公告)日：2013-04-18

申请号：US13540591

申请日：2012-07-02

Applicant: Martin Voogel ,  Steven Teig ,  Thomas S. Chanack ,  Andrew Caldwell ,  Jung Ko ,  Trevis Chandler

Inventor： Martin Voogel ,  Steven Teig ,  Thomas S. Chanack ,  Andrew Caldwell ,  Jung Ko ,  Trevis Chandler

IPC: H03K19/173

CPC classification number: H03K19/177 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H03K19/018585 ,  H03K19/17704 ,  H03K19/17744 ,  H03K19/17748 ,  H03K19/1776 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An integrated circuit (“IC”) having configurable logic circuits for configurably performing multiple different logic operations based on configuration data is provided. The IC includes a row of the configurable logic circuits and multiple configuration retrieval circuits for providing configuration bits to the row of configurable logic circuits. The IC also includes a row configuration controller for forcing the multiple configuration retrieval circuits to output a particular configuration value based on a user signal that is received at runtime.

Abstract translation: 提供具有可配置逻辑电路的集成电路（“IC”），用于基于配置数据可配置地执行多个不同的逻辑操作。 该IC包括一行可配置逻辑电路和多个配置检索电路，用于向配置逻辑电路行提供配置位。 IC还包括行配置控制器，用于强制多个配置检索电路基于在运行时接收的用户信号来输出特定配置值。

公开(公告)号：US08760193B2

公开(公告)日：2014-06-24

申请号：US13540591

申请日：2012-07-02

Applicant: Martin Voogel ,  Steven Teig ,  Thomas S. Chanack ,  Andrew Caldwell ,  Jung Ko ,  Trevis Chandler

Inventor： Martin Voogel ,  Steven Teig ,  Thomas S. Chanack ,  Andrew Caldwell ,  Jung Ko ,  Trevis Chandler

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/177 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H03K19/018585 ,  H03K19/17704 ,  H03K19/17744 ,  H03K19/17748 ,  H03K19/1776 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An integrated circuit (“IC”) having configurable logic circuits for configurably performing multiple different logic operations based on configuration data is provided. The IC includes a row of the configurable logic circuits and multiple configuration retrieval circuits for providing configuration bits to the row of configurable logic circuits. The IC also includes a row configuration controller for forcing the multiple configuration retrieval circuits to output a particular configuration value based on a user signal that is received at runtime.

Abstract translation: 提供具有可配置逻辑电路的集成电路（“IC”），用于基于配置数据可配置地执行多个不同的逻辑操作。 该IC包括一行可配置逻辑电路和多个配置检索电路，用于向配置逻辑电路行提供配置位。 IC还包括行配置控制器，用于强制多个配置检索电路基于在运行时接收的用户信号来输出特定配置值。

公开(公告)号：US08941409B2

公开(公告)日：2015-01-27

申请号：US13540596

申请日：2012-07-02

Applicant: Martin Voogel ,  Steven Teig ,  Trevis Chandler

Inventor： Martin Voogel ,  Steven Teig ,  Trevis Chandler

IPC: H03K19/177

CPC classification number: H03K19/177 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H03K19/018585 ,  H03K19/17704 ,  H03K19/17744 ,  H03K19/17748 ,  H03K19/1776 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An integrated circuit (“IC”) having configurable logic circuits for configurably performing multiple different logic operations based on configuration data is provided. The IC includes a configurable routing fabric for configurably routing signals among configurable logic circuits. The configurable routing fabric includes a particular wiring path that connects an output of a source circuit to inputs of a destination circuit. The particular wiring path includes a first path and a second path that is parallel to the first path. The first and second paths are for configurably storing output signals of the source circuit. The first path connects to a first input of the destination circuit and the second path connects to a second input of the destination path.

Abstract translation: 提供具有可配置逻辑电路的集成电路（“IC”），用于基于配置数据可配置地执行多个不同的逻辑操作。 该IC包括可配置的布线结构，用于在可配置逻辑电路之间可配置地路由信号。 可配置路由布线包括将源电路的输出连接到目的地电路的输入的特定布线路径。 特定布线路径包括平行于第一路径的第一路径和第二路径。 第一和第二路径用于可配置地存储源电路的输出信号。 第一路径连接到目的地电路的第一输入端，第二路径连接到目的地路径的第二输入端。

公开(公告)号：US20130093461A1

公开(公告)日：2013-04-18

申请号：US13540596

申请日：2012-07-02

Applicant: Martin Voogel ,  Steven Teig ,  Trevis Chandler

Inventor： Martin Voogel ,  Steven Teig ,  Trevis Chandler

IPC: H03K19/173

CPC classification number: H03K19/177 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H03K19/018585 ,  H03K19/17704 ,  H03K19/17744 ,  H03K19/17748 ,  H03K19/1776 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An integrated circuit (“IC”) having configurable logic circuits for configurably performing multiple different logic operations based on configuration data is provided. The IC includes a configurable routing fabric for configurably routing signals among configurable logic circuits. The configurable routing fabric includes a particular wiring path that connects an output of a source circuit to inputs of a destination circuit. The particular wiring path includes a first path and a second path that is parallel to the first path. The first and second paths are for configurably storing output signals of the source circuit. The first path connects to a first input of the destination circuit and the second path connects to a second input of the destination path.

Abstract translation: 提供具有可配置逻辑电路的集成电路（“IC”），用于基于配置数据可配置地执行多个不同的逻辑操作。 该IC包括可配置的布线结构，用于在可配置逻辑电路之间可配置地路由信号。 可配置路由布线包括将源电路的输出连接到目的地电路的输入的特定布线路径。 特定布线路径包括平行于第一路径的第一路径和第二路径。 第一和第二路径用于可配置地存储源电路的输出信号。 第一路径连接到目的地电路的第一输入端，第二路径连接到目的地路径的第二输入端。

公开(公告)号：US08674721B2

公开(公告)日：2014-03-18

申请号：US13119433

申请日：2009-02-11

Applicant: Jason Redgrave ,  Martin Voogel ,  Steven Teig

Inventor： Jason Redgrave ,  Martin Voogel ,  Steven Teig

IPC: H03K19/173

CPC classification number: H03K19/17736 ,  H03K19/173 ,  H03K19/1776

Abstract: An integrated circuit (‘IC’) that includes a configurable routing fabric with controllable storage elements is described. The routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric may provide the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component may continually perform operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or a distribute signals throughout the IC.

Abstract translation: 描述了包括具有可控存储元件的可配置布线结构的集成电路（'IC'）。 路由结构提供了将信号路由到源节点和目的地组件之间的通信路径。 路由结构可以提供选择性地将通过路由结构的信号存储在路由结构的存储元件内的能力。 以这种方式，源或目的地组件可以连续地执行操作（例如，计算或路由），而不管来自或来自这样的组件的先前信号是否存储在路由结构内。 源和目标组件包括可配置逻辑电路，可配置互连电路以及在整个IC中接收或分配信号的各种其它电路。

公开(公告)号：US08456190B2

公开(公告)日：2013-06-04

申请号：US13049887

申请日：2011-03-16

Applicant: Jason Redgrave ,  Martin Voogel ,  Steven Teig

Inventor： Jason Redgrave ,  Martin Voogel ,  Steven Teig

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/173 ,  H03K19/1776

Abstract: An integrated circuit (“IC”) that includes a configurable routing fabric with controllable storage elements is described. The routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric may provide the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component may continually perform operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the IC.

Abstract translation: 描述了包括具有可控存储元件的可配置路由结构的集成电路（“IC”）。 路由结构提供了将信号路由到源节点和目的地组件之间的通信路径。 路由结构可以提供选择性地将通过路由结构的信号存储在路由结构的存储元件内的能力。 以这种方式，源或目的地组件可以连续地执行操作（例如，计算或路由），而不管来自或来自这样的组件的先前信号是否存储在路由结构内。 源和目标组件包括可配置逻辑电路，可配置互连电路以及在整个IC中接收或分配信号的各种其他电路。

公开(公告)号：US20110221471A1

公开(公告)日：2011-09-15

申请号：US13049887

申请日：2011-03-16

Applicant: Jason Redgrave ,  Martin Voogel ,  Steven Teig

Inventor： Jason Redgrave ,  Martin Voogel ,  Steven Teig

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/173 ,  H03K19/1776

Abstract: An integrated circuit (“IC”) that includes a configurable routing fabric with controllable storage elements is described. The routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric may provide the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component may continually perform operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the IC.

Abstract translation: 描述了包括具有可控存储元件的可配置路由结构的集成电路（“IC”）。 路由结构提供了将信号路由到源节点和目的地组件之间的通信路径。 路由结构可以提供选择性地将通过路由结构的信号存储在路由结构的存储元件内的能力。 以这种方式，源或目的地组件可以连续地执行操作（例如，计算或路由），而不管来自或来自这样的组件的先前信号是否存储在路由结构内。 源和目标组件包括可配置逻辑电路，可配置互连电路以及在整个IC中接收或分配信号的各种其他电路。

公开(公告)号：US08912820B2

公开(公告)日：2014-12-16

申请号：US13638934

申请日：2010-10-21

Applicant: Randy R. Huang ,  Martin Voogel ,  Jingcao Hu ,  Steven Teig

Inventor： Randy R. Huang ,  Martin Voogel ,  Jingcao Hu ,  Steven Teig

IPC: H03K19/173 ,  G06F17/50 ,  H03K19/177

CPC classification number: H03K19/0008 ,  G06F17/50 ,  G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  H03K19/1737 ,  H03K19/17748 ,  H03K19/17756 ,  H03K19/17784 ,  H03K19/17796

Abstract: A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration.

Abstract translation: 一种用于降低可重构集成电路中的功耗的系统和方法。 一些实施例提供了减少要重新配置的比特数的布局和路由程序。 一些实施例提供了放置和路由程序，其增加了在某些时间不需要重新配置的电路组的数量。 一些实施例包括选择性地阻止重新配置的电路。

公开(公告)号：US20130104093A1

公开(公告)日：2013-04-25

申请号：US13621125

申请日：2012-09-15

Applicant: Randy R. Huang ,  Martin Voogel ,  Jingcao Hu ,  Steven Teig

Inventor： Randy R. Huang ,  Martin Voogel ,  Jingcao Hu ,  Steven Teig

IPC: G06F17/50

CPC classification number: H03K19/0008 ,  G06F17/50 ,  G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  H03K19/1737 ,  H03K19/17748 ,  H03K19/17756 ,  H03K19/17784 ,  H03K19/17796

Abstract: A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration.

Abstract translation: 一种用于降低可重构集成电路中的功耗的系统和方法。 一些实施例提供了减少要重新配置的比特数的布局和路由程序。 一些实施例提供了放置和路由程序，其增加了在某些时间不需要重新配置的电路组的数量。 一些实施例包括选择性地阻止重配置的电路。

公开(公告)号：US20130021058A1

公开(公告)日：2013-01-24

申请号：US13638934

申请日：2010-10-21

Applicant: Randy R. Huang ,  Martin Voogel ,  Jingcao Hu ,  Steven Teig

Inventor： Randy R. Huang ,  Martin Voogel ,  Jingcao Hu ,  Steven Teig

IPC: H03K19/0175

CPC classification number: H03K19/0008 ,  G06F17/50 ,  G06F17/5054 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/78 ,  H03K19/1737 ,  H03K19/17748 ,  H03K19/17756 ,  H03K19/17784 ,  H03K19/17796

Abstract: A system and method for reducing power consumption in a reconfigurable integrated circuit. Some embodiments provide placement and routing programs that reduce the number of bits to be reconfigured. Some embodiments provide placement and routing programs that increase the number of groups of circuits that do not need reconfiguration at some times. Some embodiments include circuits that selectively block reconfiguration.