公开(公告)号：US20140210512A1

公开(公告)日：2014-07-31

申请号：US14166667

申请日：2014-01-28

申请人： Tabula, Inc.

发明人： Scott J. Weber ,  Christopher D. Ebeling ,  Andrew Caldwell ,  Steven Teig ,  Timothy J. Callahan ,  Hung Q. Nguyen ,  Shangzhi Sun ,  Shilpa V. Yeole

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  G06F17/505

摘要： A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.

摘要翻译： 公开了一种通过在IC的设计中重新缩放原始电路组来设计集成电路（“IC”）的新颖方法。 要重新定标的原始电路组包括顺序节点，组合节点和互连。 每个顺序节点与时钟的相位相关联。 该方法产生包括电路的多个复制集合的重新定标的电路集合。 每个电路副本集包括与原始电路组中的节点和互连相同的顺序节点，组合节点和互连。 每个顺序节点与时钟的相位相关联，时钟的相位是原始集合中其对应的顺序元素的相位的一小部分。 该方法将每个电路副本中的节点连接到另一个副本集中的逻辑等效节点。 该方法用重新定标的电路组替换原始电路组。