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公开(公告)号：US20220144840A1
公开(公告)日：2022-05-12
申请号：US17429115
申请日：2020-02-06
IPC分类号： C07D487/04 , C07D471/04
摘要： A compound of Formula (I) or a pharmaceutically acceptable salt thereof is described, wherein the substituents are as defined herein. Pharmaceutical compositions comprising the same and method of using the same are also described.
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公开(公告)号：US09906467B2
公开(公告)日：2018-02-27
申请号：US14739177
申请日：2015-06-15
IPC分类号： H04L12/933 , H04L12/801
CPC分类号： H04L49/109 , H04L47/10
摘要： A data communication apparatus includes a router, first and second packet producers, and a penalizer. The router is directly connected to the first and second producers. The penalizer assesses penalties against each producer whenever that producer is serviced. The penalty value depends at least in part on an expected extent to which the first producer requires service. The penalizer then accumulates penalties against each producer.
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公开(公告)号：US09031241B2
公开(公告)日：2015-05-12
申请号：US12699959
申请日：2010-02-04
IPC分类号： H04B1/7073 , G06F13/40 , H04L7/00
CPC分类号： G06F13/4022 , H04L7/00
摘要： An approach to data communication makes use of a protocol for encoding data on a serial link that provides both a run length limiting function and a frame marking function, while minimizing communication overhead over the data bearing portions of the signal, and while limiting latency introduced into the communication. In some examples, a single bit is added as a frame marker in such a way that a single bit frame marker also limits run length.
摘要翻译： 一种数据通信方法利用一种用于对串行链路上的数据进行编码的协议，该协议同时提供了游程长度限制功能和帧标记功能，同时最小化信号的数据承载部分上的通信开销，同时将限制的延迟引入 沟通。 在一些示例中，单个位被添加为帧标记，使得单个位帧标记也限制游程长度。
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公开(公告)号：US20230353959A1
公开(公告)日：2023-11-02
申请号：US18208023
申请日：2023-06-09
发明人： Lucian V. DIPIETRO , Kelley C. SHORTSLEEVES , Thomas H. MCLEAN , Alexandre LARIVEE , Fabrizio GIORDANETTO
CPC分类号： H04R25/554 , A61B5/0026 , A61B5/746 , H04R2225/55
摘要： The present disclosure relates to novel compounds and pharmaceutical compositions thereof, and methods for inhibiting the activity of PI3K-α enzymes with the compounds and compositions of the disclosure. The present disclosure further relates to, but is not limited to, methods for treating disorders associated with PI3K-α signaling with the compounds and compositions of the disclosure.
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公开(公告)号：US20230192709A1
公开(公告)日：2023-06-22
申请号：US18162127
申请日：2023-01-31
发明人： Bakary-Barry TOURÉ , Heike SCHOENHERR , Fabrizio GIORDANETTO , Demetri T. MOUSTAKAS , Bradi M. DUDSON
IPC分类号： C07D487/04 , C07D491/048 , C07D498/22 , C07D487/22 , C07D498/02 , C07D519/00
CPC分类号： C07D487/04 , C07D491/048 , C07D498/22 , C07D487/22 , C07D498/02 , C07D519/00
摘要： The present disclosure relates to novel compounds and pharmaceutical compositions thereof, and methods for inhibiting the activity of FGFR enzymes with the compounds and compositions of the disclosure. The present disclosure further relates to, but is not limited to, methods for treating disorders associated with FGFR signaling with the compounds and compositions of the disclosure.
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公开(公告)号：US10753947B2
公开(公告)日：2020-08-25
申请号：US14473386
申请日：2014-08-29
IPC分类号： G01N33/53 , G01N33/68 , C12Q1/42 , G01N33/487
摘要： In one aspect, the invention relates to a method for identifying a compound which modulates the activity of a voltage-gated protein. In certain embodiments, the voltage gate protein is a voltage-gated ion channel. In certain embodiments, the voltage-gated protein is a voltage sensitive phosphatase. In certain embodiments, the voltage-gated protein used in conjunction with the methods of the invention is modified to altered permeability or voltage sensitivity.
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7.发明申请公开(公告)号：US20130091341A1
公开(公告)日：2013-04-11
申请号：US13680962
申请日：2012-11-19
IPC分类号： G06F15/76
CPC分类号： G06F9/30 , G06F15/76 , G06F19/16 , G06F19/701
摘要： A computation system for computing interactions in a multiple-body simulation includes an array of processing modules arranged into one or more serially interconnected processing groups of the processing modules. Each of the processing modules includes storage for data elements and includes circuitry for performing pairwise computations between data elements each associated with a spatial location. Each of the pairwise computations makes use of a data element from the storage of the processing module and a data element passing through the serially interconnected processing modules. Each of the processing modules includes circuitry for selecting the pairs of data elements according to separations between spatial locations associated with the data elements.
摘要翻译： 用于计算多体仿真中的交互的计算系统包括布置在处理模块的一个或多个串联互连处理组中的处理模块阵列。 每个处理模块包括用于数据元素的存储器，并且包括用于在每个与空间位置相关联的数据元素之间执行成对计算的电路。 每个成对计算利用来自处理模块的存储的数据元素和通过串行互连的处理模块的数据元素。 每个处理模块包括用于根据与数据元素相关联的空间位置之间的分离来选择数据元素对的电路。
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公开(公告)号：US20230373952A1
公开(公告)日：2023-11-23
申请号：US18247521
申请日：2021-10-04
IPC分类号： C07D401/04 , C07D403/04 , C07D405/04 , C07D207/27 , C07D403/06 , C07D417/04 , C07D413/04 , C07D263/20 , C07D265/32 , C07D233/32
CPC分类号： C07D401/04 , C07D403/04 , C07D405/04 , C07D207/27 , C07D403/06 , C07D417/04 , C07D413/04 , C07D263/20 , C07D265/32 , C07D233/32
摘要： A compound of Formula (I), or a pharmaceutically acceptable salt thereof, is described, where the substituents are as defined herein. Pharmaceutical compositions including the same and method of using the same are also described.
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公开(公告)号：US10739354B2
公开(公告)日：2020-08-11
申请号：US15295436
申请日：2016-10-17
IPC分类号： G01N33/53 , G01N33/68 , C12Q1/42 , G01N33/487
摘要： In one aspect, the invention relates to a method for identifying a compound which modulates the activity of a voltage-gated protein. In certain embodiments, the voltage gate protein is a voltage-gated ion channel. In certain embodiments, the voltage-gated protein is a voltage sensitive phosphatase. In certain embodiments, the voltage-gated protein used in conjunction with the methods of the invention is modified to altered permeability or voltage sensitivity.
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公开(公告)号：US09384047B2
公开(公告)日：2016-07-05
申请号：US14211294
申请日：2014-03-14
发明人： J. P. Grossman , Jeffrey S. Kuskin
CPC分类号： G06F9/4881 , G06F2209/483 , G06F2209/485
摘要： An apparatus for high-performance parallel computation, includes plural computation nodes, each having dispatch units, memories in communication with the dispatch units, and processors, each of which is in communication with the memories and the dispatch units. Each dispatch unit is configured to recognize, as ready for execution, one or more computational tasks that have become ready for execution as a result of counted remote writes into the memories. Each of the dispatch units is configured to receive a dispatch request from a processor and to determine whether there exist one or more computational tasks that are both ready and available for execution by the processor.
摘要翻译： 一种用于高性能并行计算的装置，包括多个计算节点，每个计算节点具有调度单元，与调度单元通信的存储器以及处理器，每个处理器与存储器和调度单元通信。 每个调度单元被配置为识别作为准备执行的一个或多个计算任务，这些计算任务由于计数的远程写入到存储器中而已经准备好执行。 每个调度单元被配置为从处理器接收调度请求并且确定是否存在一个或多个计算任务都已经准备好并且可供处理器执行。
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