公开(公告)号：US20240275375A1

公开(公告)日：2024-08-15

申请号：US18627386

申请日：2024-04-04

申请人： pSemi Corporation

发明人： Buddhika ABESINGHA

IPC分类号： H03K17/16 ,  H03K17/687

CPC分类号： H03K17/161 ,  H03K17/165 ,  H03K17/687

摘要： Various methods and circuital arrangements for leakage reduction in MOS devices are presented. A pull-up circuit is selectively coupled to a gate of the MOS device to provide control of a voltage to the gate that is larger than a source voltage. Voltage switching circuits selectively couple different voltages to the body and/or back-gate terminals of the MOS device. During a standby mode of operation, the leakage current of the MOS device is decreased by driving the MOS device further into its subthreshold leakage region. During standby mode, a threshold voltage of the MOS device is increased by coupling a voltage higher than the source voltage to the body and/or back-gate terminals. The MOS device can be a pass device used in low dropout regulator (LDO). During standby mode, the LDO maintains output regulation by driving the MOS device further into its subthreshold leakage region and/or increasing the threshold voltage.

公开(公告)号：US20240162888A1

公开(公告)日：2024-05-16

申请号：US18056229

申请日：2022-11-16

申请人： pSemi Corporation

发明人： Buddhika ABESINGHA ,  Keith J. RAMPMEIER

IPC分类号： H03K3/012 ,  H03K3/356 ,  H03K19/0185

CPC分类号： H03K3/012 ,  H03K3/356113 ,  H03K19/018521

摘要： Methods and devices to decrease the power consumption of level shifters in the absence of input power supply are disclosed. The described devices include current mirrors that are inactive when the level shifter is in the HIGH or LOW steady state. The disclosed methods further include a delay element used to keep the power consumption low in the case of slow input power supply ramps.

公开(公告)号：US20240134401A1

公开(公告)日：2024-04-25

申请号：US18048729

申请日：2022-10-20

申请人： pSemi Corporation

发明人： Buddhika ABESINGHA

IPC分类号： G05F1/46

CPC分类号： G05F1/46

摘要： Methods and devices for a cascode current mirror with low headroom voltage are presented. According to one aspect, a gate voltage to a cascode transistor of an input leg of the current mirror is provided by a feedback block that operates from a mirrored current output by an output leg of the current mirror. The feedback block includes a feedback current mirror that outputs a mirrored current for conduction through a self-biasing diode-connected transistor that generates the gate voltage to the cascode transistor of the input leg. According to yet another aspect, the cascode current mirror includes a start-up circuit coupled between an input to the input leg and a gate of the cascode transistor of the input leg, the start-up circuit generating a start-up voltage during a transition mode of operation of the cascode current mirror. According to one aspect, a transistor is used as the start-up circuit.

公开(公告)号：US20230261652A1

公开(公告)日：2023-08-17

申请号：US17673372

申请日：2022-02-16

申请人： pSemi Corporation

发明人： Buddhika ABESINGHA ,  Gregory SZCZESZYNSKI

IPC分类号： H03K17/567 ,  H03K17/00

CPC分类号： H03K17/567 ,  H03K17/005

摘要： Circuits and methods for transmitting high-voltage (HV) static and/or switching signals via a high-voltage (HV) transmission gate controllable via low-voltage (LV) logic are presented. The HV gate includes a biasing circuit for generating a biasing voltage to gates of two series-connected HV transistors. According to one aspect, the biasing voltage is generated through a pull-up device coupled to a HV supply having a voltage level higher than a high voltage of a signal to be transmitted. According to another aspect, the biasing voltage is generated through a LV supply coupled to a diode, and a capacitor coupled between the gates and the sources of the HV transistors. When the gate is activated, the combination of the LV supply coupled to the diode and the capacitor generates a biasing voltage based on a sum of a voltage of the LV supply and an instantaneous voltage level of the signal being transmitted.

公开(公告)号：US20240231400A9

公开(公告)日：2024-07-11

申请号：US18048729

申请日：2022-10-21

申请人： pSemi Corporation

发明人： Buddhika ABESINGHA

IPC分类号： G05F1/46

CPC分类号： G05F1/46

摘要： Methods and devices for a cascode current mirror with low headroom voltage are presented. According to one aspect, a gate voltage to a cascode transistor of an input leg of the current mirror is provided by a feedback block that operates from a mirrored current output by an output leg of the current mirror. The feedback block includes a feedback current mirror that outputs a mirrored current for conduction through a self-biasing diode-connected transistor that generates the gate voltage to the cascode transistor of the input leg. According to yet another aspect, the cascode current mirror includes a start-up circuit coupled between an input to the input leg and a gate of the cascode transistor of the input leg, the start-up circuit generating a start-up voltage during a transition mode of operation of the cascode current mirror. According to one aspect, a transistor is used as the start-up circuit.

公开(公告)号：US20230163676A1

公开(公告)日：2023-05-25

申请号：US17455671

申请日：2021-11-19

申请人： pSemi Corporation

发明人： Buddhika ABESINGHA ,  Gregory SZCZESZYNSKI

IPC分类号： H02M1/32 ,  H02M3/158 ,  H02M1/00

CPC分类号： H02M1/32 ,  H02M3/158 ,  H02M1/0095 ,  H02M1/0009 ,  H02M3/07

摘要： Disclosed embodiments may include a power converter having a power conversion circuit and a protection circuit. The power conversion circuit is electrically coupled between a first terminal and a second terminal, to convert a first voltage from the first terminal to a second voltage outputted at the second terminal. The protection circuit is electrically coupled between an input terminal of the power converter and the first terminal. The protection circuit includes a first protection device and a clamping circuit. The first protection device withstands an input voltage of the power converter to continue an operation of the power conversion circuit when the input voltage exceeds a voltage threshold value. The clamping circuit is electrically coupled to a control terminal of the first protection device to clamp a control voltage of the first protection device.

公开(公告)号：US20220224228A1

公开(公告)日：2022-07-14

申请号：US17594893

申请日：2020-05-02

申请人： pSemi Corporation

发明人： Buddhika ABESINGHA ,  Arezu BAGHERI

IPC分类号： H02M3/07 ,  H03K17/687 ,  H02M1/08 ,  H03K17/06

摘要： A power converter includes a charge pump in which transistors transition between conducting and non-conducting states thereby causing said pump capacitors to be interconnected in different arrangements at different times. Among the transistors is one that transitions into a conducting state when a source and gate of that transistor are at equal potentials.