Abstract:
A mounting structure of a three-cylinder engine is mounted in a car body transversely but is installed on engine and transmission mounts built on opposing sides in the width direction of the vehicle so that its weight can be supported, wherein a roll mount controls roll moment. The center of mass of the engine and the transmission is the center of rotation where a longitudinal pitch axis, a lateral roll axis and a vertical yaw axis all cross each other, but the roll mount is combined with the engine or the transmission so that the combination point lies on the yaw axis. The mounting structure can improve the NVH performance by suppressing the pitch moment and inducing the yaw moment and by more efficiently insulating the vibration caused by the yaw moment while maintaining the common platform.
Abstract:
Provided is a programmable logic block of a field-programmable gate array (FPGA). The programmable logic block includes a pull-up access transistor connected to a power source, an up-phase-change memory device connected to the pull-up access transistor, a down-phase-change memory device connected to the up-phase-change memory device, an output terminal between the up-phase-change memory device and the down-phase-change memory device, and a pull-down access transistor connected to the down-phase-change memory device and a ground. The resistance values of the up-phase-change memory device and the down-phase-change memory device are individually programmed.
Abstract:
A touch screen panel having first sensing electrodes including a plurality of first sensing cells arranged on a substrate and a first coupling unit that electrically couples adjacent ones of the first sensing cells, and having second sensing electrodes including a plurality of second sensing cells arranged on the substrate and a second coupling unit that electrically couples adjacent ones of the second sensing cells. The second coupling unit includes a plurality of relay patterns and the relay patterns are positioned in the first sensing electrodes.
Abstract:
A liquid crystal display device (LCD), and a method of driving the LCD. The LCD includes: a display panel including a plurality of pixels defined as a plurality of gate lines and a plurality of data lines cross each other, wherein a storage capacitor of each of the plurality of pixels is connected to a front or rear gate line; a gate driver for generating a gate-on voltage by boosting a first input voltage in multi-stages, the gate-on voltage turns on a switching device of each of the plurality of pixels, and a gate-off voltage that turns off the switching device, and sequentially applying the gate-on voltage and the gate-off voltage to the plurality of gate lines; and a source driver for applying a data voltage to a data line connected to a pixel whose switching device is turned on.
Abstract:
A liquid crystal display device (LCD), and a method of driving the LCD. The LCD includes: a display panel including a plurality of pixels defined as a plurality of gate lines and a plurality of data lines cross each other, wherein a storage capacitor of each of the plurality of pixels is connected to a front or rear gate line; a gate driver for generating a gate-on voltage by boosting a first input voltage in multi-stages, the gate-on voltage turns on a switching device of each of the plurality of pixels, and a gate-off voltage that turns off the switching device, and sequentially applying the gate-on voltage and the gate-off voltage to the plurality of gate lines; and a source driver for applying a data voltage to a data line connected to a pixel whose switching device is turned on.
Abstract:
Provided is a programmable logic block of a field-programmable gate array (FPGA). The programmable logic block includes a pull-up access transistor connected to a power source, an up-phase-change memory device connected to the pull-up access transistor, a down-phase-change memory device connected to the up-phase-change memory device, an output terminal between the up-phase-change memory device and the down-phase-change memory device, and a pull-down access transistor connected to the down-phase-change memory device and a ground. The resistance values of the up-phase-change memory device and the down-phase-change memory device are individually programmed.
Abstract:
Disclosed is an apparatus for measuring biodegradability of a polymer sample by non-dispersive infrared spectrometry, including a compression pump (2), a first air controlling unit (4), carbon dioxide removing devices (6), a filter (8), a first cooling device (10), at least two composting vessels (12), at least two second cooling devices (10′), at least two second air controlling units (14), at least two non-dispersive infrared gas analyzers 16 and collection units (18), connected in order, and a computer (34) connected to the first air controlling unit, the second air controlling units and the gas analyzers. Using the current apparatus, the amount of carbon dioxide is rapidly, quantitatively and reproducibly measured, and the apparatus is thus used for research and development procedures of biodegradable polymers.
Abstract:
A method of detecting a partial discharge signals occurring at an insulator, using a Frequency Spectrum Analyzer (FSA) with a monitor screen. The method including the steps of setting a horizontal axis of the monitor screen as a time axis and a vertical axis as an axis representing a voltage magnitude; receiving a power frequency signal having phase angle and carrying the partial discharge signals derived from the insulator being tested, to display the magnitudes of the partial discharge signals based on the time axis; detecting each of the maximum value of the partial discharge signals being displayed by the receiving step, to cause them to be evaluated into coordinate values of the horizontal axis and the vertical axis discriminating each of the phase angles of the power frequency signal based on the coordinate value of the horizontal axis detected by the detecting step, and evaluating each of the magnitudes of the partial discharge signals positioned at respective phase angles of the power frequency signal based on the coordinate value of the vertical axis; and overlapping each the phase angle of the partial discharge signals positioned at the respective phase angles evaluated by the discriminating step with each other according to corresponding phase angles, and comparing them relative to each other, such that the magnitude and number of the partial discharge signals appearing at the respective phase angles of the power frequency signal can be evaluated.