公开(公告)号：US08260246B1

公开(公告)日：2012-09-04

申请号：US12139979

申请日：2008-06-16

申请人： Yingxuan Li ,  Qing Yang

发明人： Yingxuan Li ,  Qing Yang

IPC分类号： H04B1/16

CPC分类号： H03H11/1291 ,  G11B20/10046 ,  G11B2220/2516 ,  G11B2220/2562 ,  H03H7/0153 ,  H03H19/008 ,  H03H2210/046

摘要： The following embodiments relate to an analog filter having an adjustable transfer function for use in a system or circuit that processes a signal having a changing data rate. The transfer function may be adjusted by adjusting the resistance and/or capacitance of components of the analog filter. The analog filter is calibrated based on an optimum operational parameter at a certain data rate, such as a median data rate. The analog filter may be further adjusted as the data rate of the signal changes.

摘要翻译： 以下实施例涉及具有可调节传递函数的模拟滤波器，用于处理具有变化的数据速率的信号的系统或电路中。 可以通过调整模拟滤波器的组件的电阻和/或电容来调节传递函数。 模拟滤波器基于一定数据速率下的最佳操作参数（如中值数据速率）进行校准。 随着信号的数据速率的变化，可以进一步调节模拟滤波器。

公开(公告)号：US08026742B1

公开(公告)日：2011-09-27

申请号：US12860440

申请日：2010-08-20

申请人： Pantas Sutardja ,  Christopher L. Painter ,  Yingxuan Li ,  Qing Yang

发明人： Pantas Sutardja ,  Christopher L. Painter ,  Yingxuan Li ,  Qing Yang

IPC分类号： H03D13/00

CPC分类号： H03D13/00

摘要： In one embodiment, a phase detector is provided comprising a first input, a second input, and first circuitry in communication with the first and second inputs, the first circuitry operative to provide an indication of a phase difference between a first signal supplied by the first input and a second signal supplied by the second input, wherein an aberration in one of the first and second signals results in an incorrect indication of phase difference. The phase detector also comprises second circuitry in communication with the first circuitry, the second circuitry operative to provide a correct indication of phase difference despite the aberration in the at least one of the first and second signals. In another embodiment, a differential phase detector is provided.

摘要翻译： 在一个实施例中，提供了一种相位检测器，包括第一输入端，第二输入端和与第一和第二输入端通信的第一电路，第一电路用于提供由第一输入端提供的第一信号之间的相位差的指示， 输入和由第二输入提供的第二信号，其中第一和第二信号之一中的像差导致相位差的不正确指示。 相位检测器还包括与第一电路通信的第二电路，第二电路可操作以提供相位差的正确指示，尽管第一和第二信号中的至少一个信号中存在像差。 在另一个实施例中，提供差分相位检测器。

公开(公告)号：US08498606B1

公开(公告)日：2013-07-30

申请号：US13601253

申请日：2012-08-31

申请人： Yingxuan Li ,  Qing Yang

发明人： Yingxuan Li ,  Qing Yang

IPC分类号： H04B1/16

CPC分类号： H03H11/1291 ,  G11B20/10046 ,  G11B2220/2516 ,  G11B2220/2562 ,  H03H7/0153 ,  H03H19/008 ,  H03H2210/046

摘要： The following embodiments relate to an analog filter having an adjustable transfer function for use in a system or circuit that processes a signal having a changing data rate. The transfer function may be adjusted by adjusting the resistance and/or capacitance of components of the analog filter. The analog filter is calibrated based on an optimum operational parameter at a certain data rate, such as a median data rate. The analog filter may be further adjusted as the data rate of the signal changes.

摘要翻译： 以下实施例涉及具有可调节传递函数的模拟滤波器，用于处理具有变化的数据速率的信号的系统或电路中。 可以通过调整模拟滤波器的组件的电阻和/或电容来调节传递函数。 模拟滤波器基于一定数据速率下的最佳操作参数（如中值数据速率）进行校准。 随着信号的数据速率的变化，可以进一步调节模拟滤波器。

公开(公告)号：US07791378B1

公开(公告)日：2010-09-07

申请号：US11518115

申请日：2006-09-08

申请人： Pantas Sutardja ,  Christopher L. Painter ,  Yingxuan Li ,  Qing Yang

发明人： Pantas Sutardja ,  Christopher L. Painter ,  Yingxuan Li ,  Qing Yang

IPC分类号： H03D13/00

CPC分类号： H03D13/00

摘要： In one embodiment, a phase detector is provided comprising a first input, a second input, and first circuitry in communication with the first and second inputs, the first circuitry operative to provide an indication of a phase difference between a first signal supplied by the first input and a second signal supplied by the second input, wherein an aberration in one of the first and second signals results in an incorrect indication of phase difference. The phase detector also comprises second circuitry in communication with the first circuitry, the second circuitry operative to provide a correct indication of phase difference despite the aberration in the at least one of the first and second signals. In another embodiment, a differential phase detector is provided.

摘要翻译： 在一个实施例中，提供了一种相位检测器，包括第一输入端，第二输入端和与第一和第二输入端通信的第一电路，第一电路用于提供由第一输入端提供的第一信号之间的相位差的指示， 输入和由第二输入提供的第二信号，其中第一和第二信号之一中的像差导致相位差的不正确指示。 相位检测器还包括与第一电路通信的第二电路，第二电路可操作以提供相位差的正确指示，尽管第一和第二信号中的至少一个信号中存在像差。 在另一个实施例中，提供差分相位检测器。

公开(公告)号：US08614592B1

公开(公告)日：2013-12-24

申请号：US12764578

申请日：2010-04-21

申请人： Qiang Luo ,  Yingxuan Li ,  Sriharsha Annadore ,  Pantas Sutardja

发明人： Qiang Luo ,  Yingxuan Li ,  Sriharsha Annadore ,  Pantas Sutardja

IPC分类号： H03K5/153

CPC分类号： G11B20/10009 ,  G01R19/04 ,  G11B20/10416 ,  G11B2220/2516 ,  G11B2220/2562

摘要： To detect the peaks level of an incoming signal, the difference between the voltage level of the incoming signal and a voltage developed across a capacitor is amplified. The amplified difference signal is applied to a transconductor adapted to vary its output current in response to changes in the amplified difference signal. The variations in the current generated by the transconductor are used to change a current flowing through a current mirror that charges the capacitor. The voltage developed across the capacitor represents the detected peak. The capacitor is discharged to a predefined voltage level during the reset periods. A second amplifier receiving the capacitor voltage is optionally used to develop a voltage across a second capacitor that is not reset and thus carries only the detected peak levels.

摘要翻译： 为了检测输入信号的峰值电平，输入信号的电压电平和电容器两端产生的电压之间的差异被放大。 放大的差分信号被施加到适于根据放大的差分信号的变化改变其输出电流的跨导体。 由跨导体产生的电流的变化用于改变流经电容器的电流镜的电流。 电容器上产生的电压表示检测到的峰值。 电容器在复位期间被放电到预定的电压电平。 可选地，接收电容器电压的第二放大器用于在不复位的第二电容器上产生电压，并因此仅传送检测到的峰值电平。

公开(公告)号：US08599058B1

公开(公告)日：2013-12-03

申请号：US13196368

申请日：2011-08-02

申请人： Yingxuan Li

发明人： Yingxuan Li

IPC分类号： H03M1/34

CPC分类号： H03M1/002 ,  H03M1/00 ,  H03M1/0607 ,  H03M1/0678 ,  H03M1/12 ,  H03M1/361

摘要： Systems, methods and computer program products for correcting polarity decision associated with a polarity comparator in an analog-to-digital converter are described. The polarity comparator may perform polarity decision to determine whether an analog signal is greater or smaller than zero. If the voltage difference is greater than zero, then the analog signal may be output to other comparators without polarity inversion. If the voltage difference is smaller than zero, then the signal polarity of the analog signal may be inverted before being output to other comparators. One or more redundant comparators also may be used to correct offsets of the polarity comparator to reduced errors associated with the polarity decision.

摘要翻译： 描述了用于校正与模拟 - 数字转换器中的极性比较器相关联的极性判定的系统，方法和计算机程序产品。 极性比较器可以执行极性判定以确定模拟信号是大于还是小于零。 如果电压差大于零，则模拟信号可以输出到其他比较器而不会极性反转。 如果电压差小于零，则模拟信号的信号极性可能在输出到其他比较器之前被反相。 还可以使用一个或多个冗余比较器来校正极性比较器的偏移以减少与极性判定相关联的误差。

公开(公告)号：US08331206B1

公开(公告)日：2012-12-11

申请号：US12972733

申请日：2010-12-20

申请人： Yingxuan Li ,  Fu-Tai An ,  Yonghua Song

发明人： Yingxuan Li ,  Fu-Tai An ,  Yonghua Song

IPC分类号： G11B7/00

CPC分类号： G11B7/0945

摘要： In an apparatus for conditioning a signal from an optical pickup unit (OPU), a single-ended channel includes a first signal processing block to calibrate a dark level of a single-ended signal corresponding to a single-ended output of the OPU, if any, and to center the single-ended signal. A dual-ended channel includes a second signal processing block to calibrate a dark level of a dual-ended signal corresponding to a dual-ended output of the OPU, if any, and to center the dual-ended signal. A multiplexer selects one of the single-ended channel and the dual-ended channel, and outputs a selected signal. A digital signal processing stage converts the selected signal to a digital signal.

摘要翻译： 在用于调节来自光学拾取单元（OPU）的信号的装置中，单端通道包括第一信号处理块，用于校准对应于OPU的单端输出的单端信号的暗电平，如果 任何，并将中心的单端信号。 双端通道包括第二信号处理块，用于校准对应于OPU的双端输出的双端信号的暗电平（如果有的话），并使双端信号居中。 复用器选择单端信道和双端信道之一，并输出所选信号。 数字信号处理级将选择的信号转换为数字信号。

公开(公告)号：US20050184896A1

公开(公告)日：2005-08-25

申请号：US11114326

申请日：2005-04-26

申请人： Yingxuan Li

发明人： Yingxuan Li

IPC分类号： G11C29/02 ,  H03M1/66

CPC分类号： G11C29/022 ,  G11C7/1057 ,  G11C29/02 ,  G11C29/028 ,  G11C2029/5006 ,  G11C2207/2254

摘要： A circuit, apparatus and method for efficiently and accurately calibrating an output driver current are provided in embodiments of the present invention. In an embodiment of the present invention, a circuit comprises a first digital-to-analog converter (“DAC”) that generates a first current. A first transistor is coupled to the first DAC and generates a first biasing current responsive to the first current. A second DAC is coupled to the first transistor and generates a first control current responsive to the first biasing current. According to an embodiment of the present invention, the first and second DACs are binary weighted control DACs. According to an embodiment of the present invention, the binary weighted values of the second DAC are obtained in response to a calibration signal generated by a controller. According to an embodiment of the present invention, the first DAC is an M-bit DAC and the second DAC is an N-bit DAC, wherein M is less than N. According to an embodiment of the present invention, the circuit is in a memory device and a controller generates calibration signals.

公开(公告)号：US07881172B1

公开(公告)日：2011-02-01

申请号：US12853337

申请日：2010-08-10

申请人： Pantas Sutardja ,  Yingxuan Li ,  Daniel Mumford

发明人： Pantas Sutardja ,  Yingxuan Li ,  Daniel Mumford

IPC分类号： G11B7/00

CPC分类号： G11B7/126 ,  G11B7/0062

摘要： A driver includes a parameter generation module configured to generate timing parameters based upon a received bit stream. A timing encoding module is configured to determine a plurality of pulse defining parameters based on the timing parameters. A pulse generation module is configured to determine a plurality of generic pulses based on the plurality of pulse defining parameters. The pulse generation module is configured to combine the plurality of generic pulses into a plurality of enable signals. The pulse generation module is configured to selectively invert a first enable signal of the plurality of enable signals. The pulse generation module is configured to output the plurality of enable signals including the first enable signal to a laser driver.

摘要翻译： 驱动器包括被配置为基于接收到的比特流来生成定时参数的参数生成模块。 定时编码模块被配置为基于定时参数确定多个脉冲定义参数。 脉冲发生模块被配置为基于多个脉冲定义参数来确定多个通用脉冲。 脉冲发生模块被配置为将多个通用脉冲组合成多个使能信号。 脉冲发生模块被配置为选择性地反转多个使能信号的第一使能信号。 脉冲发生模块被配置为向激光驱动器输出包括第一使能信号的多个使能信号。

公开(公告)号：US07242224B1

公开(公告)日：2007-07-10

申请号：US10990216

申请日：2004-11-15

申请人： Yingxuan Li ,  Pantas Sutardja

发明人： Yingxuan Li ,  Pantas Sutardja

IPC分类号： H03B21/00

CPC分类号： H03L7/18 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/0991 ,  H03L7/23

摘要： Circuitry and methods are provided for continuously adjustable frequency synthesis. The synthesis covers a wide range of possible frequencies and can be performed to a high degree of precision. In an embodiment of the invention, an analog phase-locked loop (“PLL”) performs relatively coarse wide-range frequency synthesis, while a digital PLL performs relatively fine narrow-range frequency synthesis and phase alignment. The analog PLL is capable of varying frequency in a stepwise linear fashion. The digital PLL communicates with the analog PLL to ensure that the output of the analog PLL is within the digital PLL's specified pull-in range.