公开(公告)号：US5663091A

公开(公告)日：1997-09-02

申请号：US644335

申请日：1996-05-09

申请人： Yeouchung Yen ,  Shih-Oh Chen ,  Hung-Kwei Hu

发明人： Yeouchung Yen ,  Shih-Oh Chen ,  Hung-Kwei Hu

IPC分类号： H01L23/525 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A method for fabricating the antifuse of the present invention comprises the steps of forming a lower antifuse electrode; forming a relatively thick interlayer dielectric layer over the surface of the lower antifuse electrode; forming a masking layer, preferably a photoresist, including an aperture therein having a first area over the interlayer dielectric layer; performing a first vertical etching step on the interlayer dielectric layer to a first selected depth; enlarging the aperture in the masking layer until it has a second area; performing a final vertical etching step on the interlayer dielectric layer to expose the upper surface of the lower electrode. Depending on the thickness of the interlayer dielectric, additional enlarging steps and vertical etching steps may be performed prior to the final vertical etching step which exposes the upper surface of the lower electrode. An aperture having a staircase profile is thereby formed, the aperture having a number of steps thus reducing and/or eliminating cusping and/or thinning at the corner and bottom of the antifuse cell opening allowing for the uniform deposit of dielectric and upper antifuse electrode materials.

摘要翻译： 制造本发明的反熔丝的方法包括以下步骤：形成下反熔丝电极; 在所述下部反熔丝电极的表面上形成相对较厚的层间电介质层; 形成掩模层，优选光致抗蚀剂，包括其中具有在所述层间介质层上的第一区域的孔; 在所述层间电介质层上进行第一垂直蚀刻步骤至第一选定深度; 扩大掩模层中的孔径，直到其具有第二区域; 在层间电介质层上进行最终的垂直蚀刻步骤以暴露下电极的上表面。 取决于层间电介质的厚度，可以在暴露下电极的上表面的最终垂直蚀刻步骤之前执行附加的放大步骤和垂直蚀刻步骤。 由此形成具有阶梯轮廓的孔，所述孔具有多个步骤，从而减少和/或消除了在反熔丝电池开口的角落和底部的捣实和/或变薄，从而均匀地沉积介电层和上部反熔丝电极材料 。

公开(公告)号：US5550404A

公开(公告)日：1996-08-27

申请号：US292801

申请日：1994-08-10

申请人： Yeouchung Yen ,  Shih-Oh Chen ,  Hung-Kwei Hu

发明人： Yeouchung Yen ,  Shih-Oh Chen ,  Hung-Kwei Hu

IPC分类号： H01L23/525 ,  H01L29/04 ,  H01L27/10 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

摘要： An antifuse comprises a lower electrode and an upper electrode separated by an interlayer dielectric. An antifuse cell opening is disposed in the interlayer dielectric. The antifuse cell opening comprises at least two steps, wherein a first portion thereof has a first area and a second portion thereof disposed above the first portion has a second area larger than said first area. Additional portions may be provided above the second portion having successively larger areas if the thickness of the interlayer dielectric warrants their inclusion.

摘要翻译： 反熔丝包括由层间电介质隔开的下电极和上电极。 反熔丝电池开口设置在层间电介质中。 反熔丝电池开口包括至少两个步骤，其中其第一部分具有第一区域，并且设置在第一部分上方的第二部分具有大于所述第一区域的第二区域。 如果层间电介质的厚度保证其包含，则可以在第二部分上方设置附加部分，其具有相继较大的面积。

公开(公告)号：US06784110B2

公开(公告)日：2004-08-31

申请号：US10263019

申请日：2002-10-01

申请人： Jianping Wen ,  Meihua Shen ,  Hung-Kwei Hu

发明人： Jianping Wen ,  Meihua Shen ,  Hung-Kwei Hu

IPC分类号： H01L21302

CPC分类号： H01L21/32137

摘要： In a method of etching a substrate, a substrate is provided in a process zone, the substrate having a pattern of features comprising dielectric covering semiconductor. In a first stage, an energized first etching gas is provided in the process zone, the energized first etching gas having a first selectivity of etching dielectric to semiconductor of at least about 1.8:1, wherein the dielectric is etched preferentially to the semiconductor to etch through the dielectric to at least partially expose the semiconductor. In a second stage, an energized second etching gas is provided in the process zone, the energized second etching gas having a second selectivity of etching dielectric to semiconductor of less than about 1:1.8, wherein the semiconductor is etched preferentially to the dielectric.

摘要翻译： 在蚀刻衬底的方法中，在工艺区域中设置衬底，衬底具有包括电介质覆盖半导体的特征图案。 在第一阶段中，在处理区域中提供通电的第一蚀刻气体，所激发的第一蚀刻气体具有至少约1.8:1的对半导体的蚀刻电介质的第一选择性，其中电介质优先蚀刻到半导体以蚀刻 通过电介质至少部分地暴露半导体。 在第二阶段中，在处理区域中提供通电的第二蚀刻气体，所通电的第二蚀刻气体具有小于约1：1.8的蚀刻电介质至半导体的第二选择性，其中半导体优先蚀刻到电介质。

公开(公告)号：US5223084A

公开(公告)日：1993-06-29

申请号：US796732

申请日：1991-11-25

申请人： Warren M. Uesato ,  Kwang-Leei K. Young ,  Hung-Kwei Hu ,  Paul K. Aum

发明人： Warren M. Uesato ,  Kwang-Leei K. Young ,  Hung-Kwei Hu ,  Paul K. Aum

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/768

CPC分类号： H01L21/76819 ,  H01L21/76804

摘要： During the manufacture of a semiconductor integrated circuit, contact holes or passages are formed through a non-planar insulating layer resulting from the deposition of dielectric over electrical contacts having differing profile heights from the surface of an internal layer, such as a substrate, to expose these contacts and/or provide electrical connections thereto. The passages are formed with a combination of sloped and vertical sidewall portions in which varying depth sloped portions are used to effectively planarize the dielectric layer and permit the vertical sidewall portions to have substantially identical vertical dimensions. This technique simultaneously exposes contacts with varying profile heights which thereby reduces contact damage. In addition, this technique effectively planarizes the dielectric layer, reducing the need for an additional planarization step.

摘要翻译： 在半导体集成电路的制造期间，通过非平面绝缘层形成接触孔或通道，所述非平面绝缘层是由内部层（例如基板）的表面上具有不同型材高度的电触点沉积而形成的，以暴露 这些触点和/或提供与其的电连接。 通道形成有倾斜和垂直侧壁部分的组合，其中使用变化的深度倾斜部分来有效地平坦化电介质层并允许垂直侧壁部分具有基本相同的垂直尺寸。 这种技术同时暴露具有不同型材高度的接触，从而减少接触损伤。 此外，该技术有效地平坦化介电层，减少了对附加平面化步骤的需要。

公开(公告)号：US06617216B1

公开(公告)日：2003-09-09

申请号：US10117575

申请日：2002-04-04

申请人： Hung-Kwei Hu

发明人： Hung-Kwei Hu

IPC分类号： H01L21336

CPC分类号： H01L29/66583 ,  H01L29/66545

摘要： Methods for use in fabricating integrated circuit structures. One embodiment of the present invention is a quasi-damascene gate, self-aligned source/drain method for forming a device on a substrate that includes steps of: (a) forming a gate dielectric layer over the substrate; (b) forming a first gate electrode layer over the gate dielectric layer; (c) forming a contact etch stop layer over the first gate electrode layer; (d) forming a self-aligning layer over the contact etch stop layer; and (e) forming and patterning a mask over the self-aligning layer.

摘要翻译： 用于制造集成电路结构的方法。 本发明的一个实施例是一种用于在衬底上形成器件的准大马士革栅极，自对准源/漏极法，其包括以下步骤：（a）在衬底上形成栅极电介质层; （b）在所述栅极介质层上形成第一栅电极层; （c）在所述第一栅电极层上形成接触蚀刻停止层; （d）在接触蚀刻停止层上形成自对准层; 和（e）在自对准层上形成和图案化掩模。

公开(公告)号：US5096802A

公开(公告)日：1992-03-17

申请号：US611270

申请日：1990-11-09

申请人： Hung-Kwei Hu

发明人： Hung-Kwei Hu

IPC分类号： H05K3/06 ,  G03F7/20 ,  G03F7/40 ,  H01L21/027

CPC分类号： G03F7/2022 ,  G03F7/40

摘要： A controllable feature shrinkage technique permits shrinkage of feature sizes beyond the capability of current lithographic tools by using high temperature flow to shrink the conventionally formed resist image of the feature and then deep UV exposure to stabilize the resist profile at the desired reduced size. A preliminary partial stabilization using hard bake and low intensity deep UV exposure reduces the rate of resist flow at temperature, permitting better control and repeatability of the amount of shrinkage. Feature sizes in the range of about 0.15 .mu.m may be achieved.

摘要翻译： 可控特征收缩技术允许通过使用高温流收缩特征的常规形成的抗蚀剂图像然后深度UV曝光以使所需的减小的尺寸稳定抗蚀剂轮廓，使特征尺寸的收缩超过当前光刻工具的能力。 使用硬烘烤和低强度深紫外线暴露的初步部分稳定性降低了在温度下的抗蚀剂流动速率，允许更好的控制和收缩量的重复性。 可以实现大约0.15μm的范围的特征尺寸。